IP Library Granted Patent US 7,475,219
Granted Patent B2
US 7,475,219 · App. 10/927,682 · Granted Jan 6, 2009

Serially indexing a cache memory

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Quick Facts
Patent No.
US 7,475,219
App. No.
10/927,682
Granted
Jan 6, 2009
Kind
B2
Abstract

In one embodiment, the present invention includes a method of accessing a cache memory to determine whether requested data is present. In this embodiment, the method may include indexing a cache with a first index corresponding to a first memory region size, and indexing the cache with a second index corresponding to a second memory region size. The second index may be used if the requested data is not found using the first index.

Claims (19)

1. A method comprising:

indexing a translation table of a cache with a first index of a received address corresponding to a first memory region size by querying said translation table at first locations associated with said first index;

indexing said translation table with a second index of said received address corresponding to a second memory region size by querying said translation table at second locations associated with said second index;

mapping a virtual address to a physical address based on a first match at a location associated with said first index;

mapping a virtual address to a physical address based on said first match and a second match at a location associated with said second index;

constructing said first index for a first physical address;

comparing a virtual address tag to a first array tag of said translation table;

comparing a virtual address size to a first array size of said translation table; and

constructing said second index for a second physical address based on said comparing of a virtual address tag and said comparing of a virtual address size,

wherein said translation table includes translations for mapping addresses, wherein said first index is different than said second index, and wherein said first memory region size is different than said second memory region size.

2. The method of claim 1 further comprising returning a translation address based on said comparing of said virtual address tag and said comparing of said virtual address size.

3. The method of claim 1 further comprising:

comparing said virtual address tag to a second array tag of said translation table;

comparing said virtual address size to a second array size of said translation table; and

returning a translation address based on said comparing of said virtual address tag to said second array tag and said comparing of said virtual address size to said second array size.

4. The method of claim 1 further comprising initiating a page table walk on said translation table when said virtual address tag does not match said first array tag and said second array tag.

5. The method of claim 4 wherein said page table walk comprises searching each entry in said page table for a match of said virtual address tag.

6. The method of claim 1 wherein said second size is greater than said first size.

7. The method of claim 1 wherein said constructing of said first index, said comparing of said virtual address tag, and constructing of said second index are performed consecutively.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053475/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2020
From: MARVELL INTERNATIONAL LTD.
To: CAVIUM INTERNATIONAL
Reel/Frame 052918/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2006
From: INTEL CORPORATION
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 018515/0817 →