Distributed ring control circuits for Viterbi traceback

1. A traceback memory, comprising:

a memory chip having rows and columns to store survivor transition information; and

a write shift register ring to enable columns of said memory chip during write operations by shifting a predetermined data value through said write shift register ring in a sequential manner;

a traceback shift register ring to enable columns of said memory chip during traceback read operations by shifting a predetermined data value through said traceback shift register ring in a sequential manner, wherein said predetermined data value is shifted through said traceback shift register ring in an opposite direction than said predetermined data value in said write shift register ring; and

a decode shift register ring to enable columns of said memory chip during decode operations by shifting a predetermined data value through said decode shift register ring in a sequential manner, wherein said predetermined data value is shifted through said decode shift register ring in an opposite direction than said predetermined data value in said write shift register ring.

2. The traceback memory of claim 1 , wherein:

said write shift register ring and said decode shift register ring operate at the same clock speed and said traceback shift register ring operates at a different, higher clock speed.

3. The traceback memory of claim 1 , wherein:

said predetermined data value is a logic one.

4. The traceback memory of claim 1 , wherein:

said write shift register ring includes a plurality of flip flops connected in a ring configuration.

5. The traceback memory of claim 1 , wherein:

said write shift register ring includes a plurality of data latches connected in a ring configuration.

6. The traceback memory of claim 1 , further comprising:

a row decoder to enable a selected row of said memory chip in response to a state address.

7. The traceback memory of claim 1 , further comprising:

first logic circuitry connected to said write shift register ring and said traceback shift register ring to initiate a new traceback operation based on the proximity of a traceback pointer to a write pointer.

8. The traceback memory of claim 7 , wherein:

said first logic circuitry includes an AND gate for each position in said write shift register ring.

9. The traceback memory of claim 7 , further comprising:

second logic circuitry connected to said write shift register ring and said decode shift register ring to reposition a decode pointer based on the proximity of a decode pointer to said write pointer.

10. The traceback memory of claim 9 , wherein:

said second logic circuitry includes an AND gate for each position in said write shift register ring.

11. A method comprising:

shifting a predetermined data value through a first shift register ring in a Viterbi decoder to sequentially enable columns in a traceback memory to write trellis survivor transition data to storage locations in said columns;

shifting a predetermined data value through a second shift register ring in said Viterbi decoder to sequentially enable columns in said traceback memory to perform traceback read functions for said Viterbi decoder, wherein said predetermined value is shifted through said second shift register ring in an opposite direction from said predetermined value in said first shift register ring; and

shifting a predetermined data value through a third shift register ring in said Viterbi decoder to sequentially enable columns in said traceback memory to perform decode read functions for said Viterbi decoder, wherein said predetermined value is shifted through said third shift register ring in an opposite direction from said predetermined value in said first shift register ring.

12. The method of claim 11 , wherein:

shifting a predetermined data value through said first shift register ring and shifting a predetermined data value through said third shift register ring are performed at the same clock speed and shifting a predetermined data value through said second shift register ring is performed at a different, faster clock speed.

13. The method of claim 11 , further comprising:

repositioning a decode pointer within said third shift register ring when said decode pointer is proximate to a write pointer within said first shift register ring.

14. The method of claim 11 , wherein:

said predetermined data value is a logic one.

15. The method of claim 11 , further comprising:

initiating a new traceback operation when a traceback pointer within said second shift register ring is proximate to a write pointer within said first shift register ring.

16. The method of claim 15 , wherein:

initiating a new traceback operation includes initiating said new traceback operation when said traceback pointer within said second shift register ring is at the same position as said write pointer within said first shift register ring.

17. A Viterbi decoder comprising:

a traceback memory having:

a memory chip having rows and columns to store survivor transition information;

a write shift register ring to enable columns of said memory chip during write operations by shifting a predetermined data value through said write shift register ring in a sequential manner;

a traceback shift register ring to enable columns of said memory chip during traceback read operations by shifting a predetermined data value through said traceback shift register ring in a sequential manner, wherein said predetermined data value is shifted through said traceback shift register ring in an opposite direction than said predetermined data value in said write shift register ring;

a decode shift register ring to enable columns of said memory chip during decode operations by shifting a predetermined data value through said decode shift register ring in a sequential manner, wherein said predetermined data value is shifted through said decode shift register ring in an opposite direction than said predetermined data value in said write shift register ring; and

wherein said Viterbi decoder further comprises at least one digital processing device to control the writing of survivor transition information to said traceback memory.

18. The Viterbi decoder of claim 17 , wherein:

said at least one digital processing device is configured to control the performance of traceback operations in said Viterbi decoder using information stored in said traceback memory.

19. The Viterbi decoder of claim 17 , wherein:

said at least one digital processing device is configured to control the performance of decode operations in said Viterbi decoder using information stored in said traceback memory.

20. The Viterbi decoder of claim 17 , wherein:

said at least one digital processing device comprises a digital signal processor.