Least mean square dynamic cache-locking
View Patent ↗A dynamic cache-locking algorithm may determine the most frequently used function(s) and the number of cache lines that should be locked into the instruction cache embedded into a processor. By evaluating the dynamic cache-locking algorithm, a determination may be made to lock an optimal amount of functions that correspond to a given, limited amount of instruction cache.
1. A method comprising:
running a provided service in a processor using a cache; and
selecting lines of the cache to lock in accordance with evaluating a Least-Mean-Square (LMS) based cache-locking algorithm that receives cache characteristics for the provided service.
2. The method of claim 1 further including:
using the dynamic cache-locking algorithm to lock at least one of an instruction cache, a data cache, an L2 cache or an OS-managed internal memory.
3. The method of claim 1 further including:
receiving data stored in a history table for functions corresponding to the provided service in the processor.
4. The method of claim 1 wherein evaluating the dynamic cache-locking algorithm further includes:
receiving an optimum number of cache misses for functions corresponding to the provided service in the processor.
5. The method of claim 1 wherein selecting lines of the cache to lock further includes:
selecting lines of the cache to lock corresponding to frequently used services.
6. An article comprising:
a computer-readable storage medium, the medium having stored thereon instructions, the instructions, when executed, resulting in a method of selecting lines of a cache to lock in accordance with results from evaluating a Least-Mean-Square(LMS) based algorithm that receives cache characteristics for a service provided by a processor.
7. The article of claim 6 further including:
storing data in a history table that corresponds to the service provided by the processor, the stored data used to evaluate the dynamic cache-locking algorithm.
8. The article of claim 7 further including:
providing an optimum number of cache misses for functions corresponding to the service provided by the processor for use in evaluating the dynamic cache-locking algorithm.
9. The article of claim 8 further including:
providing a number of cache-misses at time intervals to be used in evaluating the LMS based algorithm.
10. A method comprising:
utilizing a dynamic cache-locking algorithm to determine lines of a cache to lock based on a number of cache-misses in a time interval, the cache-misses being determined for a service being operated by a processor.
11. The method of claim 10 wherein utilizing a dynamic cache-locking algorithm further includes evaluating a Least Means Square (LMS) based algorithm.
12. The method of claim 11 further including:
storing data in a history table that corresponds to the service provided by the processor, the stored data used to evaluate the LMS based algorithm.
13. The method of claim 10 further including:
using the dynamic cache-locking algorithm to lock at least one of an instruction cache, a data cache, an L2 cache or an OS-managed internal memory.
14. A system comprising:
an omni-directional antenna;
a receiver coupled to the omni-directional antenna to process a modulated signal; and
a processor coupled to receive quadrature signals from the receiver, the processor having a cache where an operating system of the processor selects lines of the cache to lock in accordance with evaluating a Least-Mean-Square (LMS) based cache-locking algorithm that receives cache characteristics for a service provided by the processor.
15. The system of claim 14 , wherein a service provided by the processor is selected from at least a timer Interrupt Service Routine (ISR) service, a Direct Memory Access (DMA) service and a flush Cache service.
16. The system of claim 14 , wherein a result of the dynamic cache-locking algorithm depends on data in a stored history table that corresponds to the service provided by the processor.
17. The system of claim 14 , wherein a result of the dynamic cache-locking algorithm depends on cache-misses during set time intervals.