Predecode apparatus, systems, and methods

1. A method, comprising:

indicating a processor mode to a memory containing a plurality of predecoded instructions;

storing the processor mode in the memory; and

selecting a predecoded instruction from the plurality of predecoded instructions according to the processor mode.

2. The method of claim 1 , further comprising:

detecting a cache miss upon attempting to access the predecoded instruction in a cache when the processor mode is different than another processor mode used to create the predecoded instruction.

3. The method of claim 1 , wherein indicating the processor mode to the memory further includes:

sending the processor mode to another memory in conjunction with a cache fill request.

4. The method of claim 3 , wherein selecting a predecoded instruction further includes:

selecting a predecoder based on the processor mode.

5. The method of claim 1 , further comprising:

indicating the processor mode to a cache.

6. The method of claim 5 , further comprising:

mapping the predecoded instruction to a line in the cache selected from a plurality of lines based on the processor mode.

7. The method of claim 1 , wherein the processor mode is indicated according to at least one of resources that can be accessed, instructions that can legally be processed, and a width of an instruction.

8. An article comprising a machine-accessible medium having associated data, wherein the data, when accessed, results in a machine performing:

indicating a processor mode selected from a plurality of modes to a memory containing a plurality of instructions, wherein a first set of predecoded instructions included in the plurality of instructions corresponds to the processor mode;

storing the processor mode in the memory; and

selecting a predecoded instruction from the first set of predecoded instructions according to the processor mode.

9. The article of claim 8 , wherein the machine-accessible medium further includes data, which when accessed by the machine, results in the machine performing:

indicating a different processor mode selected from a plurality of modes to the memory, wherein a second set of instructions included in the plurality of instructions corresponds to the different processor mode; and

selecting a predecoded instruction from the second set of instructions according to the different processor mode.

10. The article of claim 8 , wherein the machine-accessible medium further includes data, which when accessed by the machine, results in the machine performing:

sending a cache fill request associated with a block of memory; and

determining a size of the block of memory based on the processor mode.

11. The article of claim 8 , wherein the machine-accessible medium further includes data, which when accessed by the machine, results in the machine performing:

storing the processor mode in a cache tag associated with a predecoding mode applied to the predecoded instruction.

12. An apparatus, comprising:

a processor to provide a modal property indicator indicating a processor mode; and

a memory to receive and store the modal property indicator and to access a selected location including a predecoded instruction based on a condition of the modal property indicator.

13. The apparatus of claim 12 , wherein the modal property indicator is a cache tag, and wherein the memory comprises a cache having a plurality of predecoded instructions associated with a plurality of indications provided by the modal property indicator.

14. The apparatus of claim 12 , further comprising:

a predecoder capable of being communicatively coupled to the memory and a memory system, wherein the predecoder is capable of predecoding an instruction included in a plurality of instructions according to the condition of the modal property indicator.

15. The apparatus of claim 12 , wherein the selected location includes a physical register included in a first set of registers if the condition comprises a first state, and wherein the selected location includes a second physical register included in a second set of registers if the condition comprises a second state.

16. The apparatus of claim 12 , wherein the selected location includes a first physical memory location included in the memory if the condition comprises a first state, and wherein the selected location includes a second physical memory location included in the memory if the condition comprises a second state.

17. A system, comprising:

a processor coupled to a cache having a cache tag to indicate a first processor mode and a second processor mode selected from a plurality of processor modes associated with the processor;

a first predecoder associated with the first processor mode and capable of being communicatively coupled to the cache;

a second predecoder associated with the second processor mode and capable of being communicatively coupled to the cache; and

a wireless communication device capable of being communicatively coupled to the processor.

18. The system of claim 17 , wherein the first predecoder is capable of detecting an illegal instruction and translating the illegal instruction into an opcode exception instruction.

19. The system of claim 17 , wherein the cache is a predecoded instruction cache, further comprising:

a memory capable of being communicatively coupled to the cache and receiving an indication of the first processor mode.

20. The system of claim 17 , wherein the first predecoder operates to generate a first internal address space different from a second internal address space generated by the second predecoder.