Storing and transferring SIMD saturation history flags and data size

1. A method comprising:

decoding a coprocessor instruction of a first instruction format identifying a saturating operation, a first source having a first plurality of packed data elements and a second source having a second plurality of packed data elements;

executing the saturating operation on the first plurality of packed data elements and the second plurality of packed data elements;

storing a plurality of saturation flags to indicate if a result of the saturating operation saturated;

decoding a transfer instruction of a second instruction format identifying a transfer operation for saturation flags, and a saturation data size;

executing the transfer operation on a set of saturation flags for the saturation data size from the plurality of saturation flags; and

storing a result to a condition code flags set of a status register.

2. The method of claim 1 wherein decoding the coprocessor instruction identifies a saturating operation selected from the group consisting of a SIMD pack operation, a SIMD add operation and a SIMD subtract operation.

3. The method of claim 2 wherein bits 11 – 5 of the first instruction format have binary values selected from the group consisting of 0001100 and 0001101.

4. The method of claim 3 wherein responsive to bits 23 – 22 of the first instruction formal having binary values 00 up to eight saturation flags are set to indicate if any of eight corresponding byte results saturated.

5. The method of claim 3 wherein responsive to bits 23 – 22 of the first instruction format having binary values 01 up to four saturation flags are set to indicate if any of corresponding 16-bit half word results saturated.

6. The method of claim 5 wherein responsive to bits 23 – 22 of the first instruction format having binary values 10, up to two saturation flags are set to indicate if any of two corresponding 32-bit word results saturated.

7. The method of claim 1 wherein bits 11 – 5 of the first instruction format have binary values 0000100.

8. The method of claim 7 wherein responsive to bit, 23 – 22 of the first instruction format having binary values 01, up to eight saturation flags in bit positions 7 – 0 of a status register are to indicate if any of eight corresponding byte results saturated.

9. The method of claim 8 wherein responsive to bits 23 – 22 of the first instruction format having binary values 10, up to four saturation flags in bit positions 7 , 5 , 3 and 1 of a status register are to indicate if any of four corresponding 16-bit half word results saturated.

10. The method of claim 9 wherein responsive to bits 23 – 22 of the first instruction format having binary values 11, up to two saturation flags an bit positions 7 and 3 of a status register are to indicate if any of two corresponding 32-bit word results saturated.

11. An article of manufacture comprising

a machine-accessible medium including data that, when accessed by a machine, cause the machine to perform the method of claim 10 .

12. The method of claim 2 wherein responsive to bits 21 – 20 of the first instruction format baying binary values 11, the plurality of saturation flags are stored to indicate if a result of signed saturating operation saturated.

13. The method of claim 2 wherein responsive to bits 21 – 20 of the first instruction format having binary values 01, the plurality of saturation flags are stored to indicate if a result of an unsigned saturating operation saturated.

14. The method of claim 1 wherein decoding the coprocessor instruction identifies a SIMD complex subtraction-addition operation or a SIMD complex addition-subtraction operation.

15. The method of claim 14 wherein up to four saturation flags in bit positions 7 , 5 , 3 and 1 of a status register are set to indicate if any of four corresponding 16-bit half word results saturated.

16. The method of claim 1 wherein decoding the coprocessor instruction identifies a SIMD mixed mode addition operation.

17. The method of claim 16 wherein responsive to bit 22 of the first instruction format having a binary value 1, up to four saturation flags in bit positions 7 – 4 of a status register are to indicate if any of four corresponding unsigned byte results saturated.

18. The method of claim 17 wherein responsive to bit 22 of the first instruction format having a binary value 0, up to four saturation flags in bit positions 3 – 0 of a status register are to indicate if any of four corresponding unsigned byte results saturated.

19. The method of claim 1 wherein decoding the coprocessor instruction identifies a SIMD fractional multiply and accumulate operation or a SIMD fractional multiply, negate and accumulate operation.

20. The method of claim 19 wherein up to two saturation flags in bit positions 7 and 3 of a status register are set to indicate if any of two corresponding 32-bit signed word results saturated.

21. The method of claim 1 wherein decoding the coprocessor instruction identifies a SIMD fractional multiply operation.

22. The method of claim 21 wherein up to two saturation flags in bit positions 7 and 3 of a status register are set to indicate if any of two corresponding 32-bit signed word results saturated.

23. The method of claim 21 wherein up to four saturation flags in bit positions 7 , 5 , 3 and 1 of a status register are set to indicate if any of four corresponding 16-bit signed half word results saturated.

24. The method of claim 1 wherein decoding the coprocessor instruction identifies a SIMD multiply and add operation.

25. The method of claim 24 wherein two saturation flags in bit positions 7 and 3 of a status register are to indicate if any of two corresponding 32-bit signed word results saturated.

26. The method of claim 24 wherein two saturation flags in bit positions 7 and 3 of a status register are to indicate if any of two corresponding 32-bit unsigned word results saturated.

27. The method of claim 1 wherein the plurality of saturation flags comprises at least eight saturation flags.

28. The method of claim 1 wherein the plurality of saturation flags comprises at least sixteen saturation flags.

29. The method of claim 1 wherein bits 11 – 5 of the first instruction format have binary values 0001010.

30. An article of manufacture comprising

a machine-accessible medium including data that, when accessed by a machine, cause the machine to perform the method of claim 1 .

31. An apparatus comprising:

a coprocessor interface unit to identify an instruction of a first instruction format for a saturating operation, a first source having a first plurality of packed data elements and a second source having a second plurality of packed data elements;

an execution unit to perform the saturating operation on the first plurality of packed data elements and the second plurality of packed data elements;

a register to store a plurality of saturation flags to indicate if a result of the saturating operation saturated;

the coprocessor interface unit to identify a transfer instruction of a second instruction format identifying a transfer operation for saturation flags, and a saturation data size;

a transfer unit to perform the transfer operation on a set of saturation flags for the saturation data size from the plurality of saturation flags; and

a status register having a condition code flags set to store the result of the transfer operation.

32. The apparatus of claim 31 , wherein bits 11 – 5 of the second instruction format have binary values 0001010.

33. The apparatus of claim 31 , wherein a logical OR of the set of saturation flags for the saturation data size is stored as the result of the transfer operation.

34. The apparatus of claim 31 wherein the register stores at least eight saturation flags that are set to indicate if any of eight corresponding byte results saturated.

35. The apparatus of claim 34 wherein the register stores at least four saturation flags that are set are set to indicate if any of four corresponding 16-bit half word results saturated.

36. The apparatus of claim 35 wherein the register stores at least two saturation flags that are set are set to indicate if any of two corresponding 32-bit word results saturated.

37. The apparatus of claim 36 wherein said at least two saturation flags to indicate if any of two corresponding 32-bit word results saturated comprise sticky saturation flags at bit positions 7 and 3 of the register.

38. The apparatus of claim 35 wherein said at least four saturation flags to indicate if any of four corresponding 16-bit half word results saturated comprise sticky saturation flags at bit positions 7 , 5 , 3 and 1 of the register.

39. The apparatus of claim 34 wherein said at least eight saturation flags to indicate if any of eight corresponding byte results saturated comprise sticky saturation flags at bit positions 7 – 0 of the register.

40. The apparatus of claim 31 wherein the instruction of the first instruction format identifies a saturating operation selected from the group consisting of a SIMD pack operation, a SIMD add operation and a SIMD subtract operation.

41. The apparatus of claim 40 wherein bits 11 – 5 of the first instruction format have binary values selected from the group consisting of 0000100, 0001100 and 0001101.

42. The apparatus of claim 31 wherein bits 11 – 5 of the first instruction format have binary values 0001110 or 0001101.

43. The apparatus of claim 42 wherein the instruction of the first instruction format identifies a SIMD complex subtraction-addition operation or a SIMD complex addition-subtraction operation.

44. The apparatus of claim 42 wherein the instruction of the first instruction format identifies a SIMD mixed mode addition operation.

45. The apparatus of claim 31 wherein the instruction of the first instruction format identifies a SIMD fractional multiply and accumulate operation or a SIMD fractional multiply, negate and accumulate operation.

46. The apparatus of claim 45 wherein bits 11 – 5 of the first instruction format have binary values 0000101.