Low-leakage level shifter with integrated firewall and method

1. A level shifter with integrated firewall comprising:

an input stage comprising input circuitry and an input stage firewall switching element, the input stage firewall switching element to either couple or decouple the input circuitry from a reference voltage in response to a firewall enable signal; and

a voltage translator stage to translate signals between a first voltage domain and a second voltage domain, the voltage translator stage comprising a firewall assertion switching element to cause the level shifter to generate an output signal having a predetermined one of either a high or low state when the firewall enable signal is asserted,

wherein the voltage translator stage translates signals between the first voltage domain and the second voltage domain when the firewall enable signal is deasserted, and

wherein the voltage translator stage further comprises firewall switching elements to couple data signal switching elements to voltage translation switching elements when the firewall enable signal is deasserted.

2. The level shifter of claim 1 further comprising an output stage comprising output circuitry to provide the output signal referenced to the second voltage domain, wherein the firewall assertion switching element asserts a predetermined signal level at an intermediate node to cause the output stage to generate the output signal having the predetermined one of either a high or low state when the firewall enable signal is asserted, the predetermined state being irrespective of the prior state of the output signal.

3. The level shifter of claim 2 wherein the input circuitry is coupled to a first supply voltage for powering circuitry external to the level shifter of the first voltage domain, and wherein the output circuitry is coupled to a second supply voltage for powering circuitry external to the level shifter of the second voltage domain, and

wherein the reference voltage (Vss) is a ground voltage.

4. The level shifter of claim 3 wherein the firewall enable signal is a signal of the second voltage domain, and

wherein when the firewall enable signal is asserted, the circuitry external to the level shifter of the first voltage domain is in a standby mode, the input circuitry no longer receives power from the first supply voltage, and the level shifter provides an output signal having a predetermined valid state.

5. The level shifter of claim 3 wherein when the firewall enable signal is asserted, the circuitry external to the level shifter of the second voltage domain is in a standby mode, the output circuitry no longer receives power from the second supply voltage, and the level shifter provides an output signal having a predetermined valid state.

6. The level shifter of claim 1 wherein when the firewall enable signal is asserted, the firewall switching elements decouple the data signal switching elements from the voltage translation switching elements to reduce leakage current in the voltage translation switching elements, and

wherein when the firewall enable signal is asserted, the input stage switching element decouples the input circuitry from the reference voltage to reduce leakage current in the input circuitry.

7. The level shifter of claim 1 wherein the voltage translation switching elements comprise back-to-back coupled transistors, and

wherein the data signal switching elements couple data signals from the input stage to an output stage.

8. The level shifter of claim 1 wherein the input stage firewall switching element comprises a high-threshold-voltage, low-leakage-current metal-oxide semiconductor (MOS) field effect transistor (FET),

wherein the firewall switching elements comprise high-threshold-voltage, low-leakage-current MOSFETs, and

wherein the firewall assertion switching element comprises a high-threshold-voltage, low-leakage-current MOSFET.

9. The level shifter of claim 8 wherein the input stage firewall switching element comprises an N-channel MOSFET, the translator stage firewall switching elements comprise N-channel MOSFETs, and the firewall assertion switching element comprises a P-channel MOSFET.

10. The level shifter of claim 8 wherein the input circuitry comprises an input inverter comprising N-channel and P-channel low-threshold-voltage, high-leakage-current MOSFETs, and

wherein the output circuitry comprises an output inverter comprising N-channel and P-channel high-threshold-voltage, low-leakage-current MOSFETs.

11. The level shifter of claim 10 wherein the high-threshold-voltage, low-leakage-current MOSFETs have at least one of either a longer channel length or a thicker gate-oxide layer than the low-threshold-voltage, high-leakage-current MOSFETs.

12. The level shifter of claim 8 wherein the data signal switching elements comprise N-channel low-threshold-voltage, high-leakage-current MOSFETs, and

wherein the voltage translation switching elements comprise P-channel high-threshold-voltage, low-leakage-current MOSFETs.

13. A method to reduce leakage current and provide firewall protection between circuits of different voltage domains when one voltage domain is in a standby mode comprising:

either coupling or decoupling input circuitry from a reference voltage in response to a firewall enable signal;

translating signals between a first voltage domain and a second voltage domain when the firewall enable signal is deasserted;

generating an output signal having a predetermined one of either a high or low state when the firewall enable signal is asserted, the predetermined state being irrespective of a prior state of the output signal;

coupling data signal switching elements to voltage translation switching elements when the firewall enable signal is deasserted;

decoupling the data signal switching elements from the voltage translation switching elements when the firewall enable signal is asserted to reduce leakage current in the voltage translation switching elements; and

decoupling the input circuitry from the reference voltage when the firewall enable signal is asserted to reduce leakage current in the input circuitry.

14. The method of claim 13 comprising decoupling the input circuitry from the reference voltage to reduce leakage current in the input circuitry when the firewall enable signal is asserted.

15. The method of claim 13 further comprising:

providing the output signal referenced to the second voltage domain at least when the firewall enable signal is deasserted; and

asserting a predetermined signal level at an intermediate node to cause an output stage to generate the output signal having the predetermined one of either a high or low state when the firewall enable signal is asserted, the predetermined state being irrespective of the prior state of the output signal.

16. An integrated circuit comprising:

first voltage domain circuitry; and

one or more level shifters with integrated firewalls to translate signals between the first voltage domain circuitry and second voltage domain circuitry,

wherein the one or more level shifters comprise:

an input stage comprising input circuitry and an input stage firewall switching element, the input stage firewall switching element to either couple or decouple the input circuitry from a reference voltage in response to a firewall enable signal; and

a voltage translator stage to translate signals between a first voltage domain and a second voltage domain, the voltage translator stage comprising a firewall assertion switching element to cause the level shifter to generate an output signal having a predetermined one of either a high or low state when the firewall enable signal is asserted,

wherein when the firewall enable signal is asserted, either the first voltage domain circuitry or the second voltage domain circuitry is in a standby mode,

wherein voltage translator stage translates signals provided by the first voltage domain circuitry between the first voltage domain and the second voltage domain when the firewall enable signal is deasserted, and

wherein the voltage translator stage further comprises firewall switching elements to couple data signal switching elements to voltage translation switching elements when the firewall enable signal is deasserted.

17. The integrated circuit of claim 16 wherein when the firewall enable signal is asserted, the firewall switching elements decouple the data signal switching elements from the voltage translation switching elements to reduce leakage current in the voltage translation switching elements, and

wherein when the firewall enable signal is asserted, the input stage switching element decouples the input circuitry from the reference voltage to reduce leakage current in the input circuitry.

18. The integrated circuit of claim 16 wherein the first voltage domain circuitry, the second voltage domain circuitry and the level shifters are fabricated on a single integrated circuit.

19. An integrated circuit comprising:

first voltage domain circuitry; and

one or more level shifters with integrated firewalls to translate signals between the first voltage domain circuitry and second voltage domain circuitry,

wherein the one or more level shifters comprise:

an input stage comprising input circuitry and an input stage firewall switching element, the input stage firewall switching element to either couple or decouple the input circuitry from a reference voltage in response to a firewall enable signal;

a voltage translator stage to translate signals between a first voltage domain and a second voltage domain, the voltage translator stage comprising a firewall assertion switching element to cause the level shifter to generate an output signal having a predetermined one of either a high or low state when the firewall enable signal is asserted;

third voltage domain circuitry;

one or more of the level shifters to translate signals between the first and third voltage domain circuitries; and

one or more of the level shifters to translate signals between the second and third voltage domain circuitries,

wherein when the firewall enable signal is asserted, either the first voltage domain circuitry or the second voltage domain circuitry is in a standby mode.

20. An integrated circuit comprising:

first voltage domain circuitry; and

one or more level shifters with integrated firewalls to translate signals between the first voltage domain circuitry and second voltage domain circuitry,

wherein the one or more level shifters comprise:

an input stage comprising input circuitry and an input stage firewall switching element, the input stage firewall switching element to either couple or decouple the input circuitry from a reference voltage in response to a firewall enable signal; and

a voltage translator stage to translate signals between a first voltage domain and a second voltage domain, the voltage translator stage comprising a firewall assertion switching element to cause the level shifter to generate an output signal having a predetermined one of either a high or low state when the firewall enable signal is asserted,

wherein when the firewall enable signal is asserted, either the first voltage domain circuitry or the second voltage domain circuitry is in a standby mode,

wherein the first voltage domain circuitry comprises a first cell having a first predetermined cell height, the second voltage domain circuitry comprises a second cell having the first predetermined cell height, and the one or more level shifters comprises cells having a second predetermined cell height, wherein the second predetermined cell height is approximately twice the first predetermined cell height,

wherein the first voltage domain circuitry is positioned within an integrated circuit between a first supply voltage rail and a reference voltage rail,

wherein the second voltage domain circuitry is positioned within the integrated circuit between a second supply voltage rail and the reference voltage rail, and

wherein at least one of the level shifters is positioned within the integrated circuit between the first and second supply voltage rails and over the reference voltage rail.

21. A machine-readable medium that provides instructions, which when executed by one or more processors, cause the processors to perform operations comprising:

either coupling or decoupling input circuitry from a reference voltage in response to a firewall enable signal;

translating signals between a first voltage domain and a second voltage domain when the firewall enable signal is deasserted;

generating an output signal having a predetermined one of either a high or low state when the firewall enable signal is asserted, the predetermined state being irrespective of a prior state of the output signal;

coupling data signal switching elements to voltage translation switching elements when the firewall enable signal is deasserted;

decoupling the data signal switching elements from the voltage translation switching elements when the firewall enable signal is asserted to reduce leakage current in the voltage translation switching elements; and

decoupling the input circuitry from the reference voltage when the firewall enable signal is asserted to reduce leakage current in the input circuitry.

22. The machine-readable medium of claim 21 wherein the instructions, when further executed by one or more of the processors cause the processors to perform operations further comprising:

decoupling the input circuitry from the reference voltage to reduce leakage current in the input circuitry when the firewall enable signal is asserted.

23. The machine-readable medium of claim 21 wherein the instructions, when further executed by one or more of the processors cause the processors to perform operations further comprising:

providing the output signal referenced to the second voltage domain at least when the firewall enable signal is deasserted; and

asserting a predetermined signal level at an intermediate node to cause the output stage to generate the output signal having the predetermined one of either a high or low state when the firewall enable signal is asserted, the predetermined state being irrespective of the prior state of the output signal.

24. A circuit for level shifting signals between voltage domains comprising:

an input stage firewall transistor to either couple or decouple an input inverter from a reference voltage in response to a firewall enable signal;

a firewall assertion transistor to generate an output signal having a predetermined state when the firewall enable signal is asserted; and

a voltage translator stage to translate signals between a first voltage domain and a second voltage domain when the firewall enable signal is deasserted, the voltage translator stage comprising the firewall assertion transistor,

wherein the voltage translator stage further comprises firewall transistors to couple data signal transistors to back-to-back coupled voltage translation transistors when the firewall enable signal is deasserted.

25. The circuit of claim 24 wherein when the firewall enable signal is asserted, the firewall transistors decouple the data signal transistors from the voltage translation transistors to reduce leakage current in the voltage translation transistors, and

wherein when the firewall enable signal is asserted, the input stage firewall transistor decouples the input inverter from the reference voltage to reduce leakage current in the input inverter.