IP Library Granted Patent US 6,897,512
Granted Patent B2
US 6,897,512 · App. 09/981,764 · Granted May 24, 2005

Device and method for protecting against oxidation of a conductive layer in said device

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Quick Facts
Patent No.
US 6,897,512
App. No.
09/981,764
Granted
May 24, 2005
Kind
B2
Abstract

In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Claims (32)

1. A semiconductor device, comprising:

a substrate;

a first conductive layer over said substrate, the first layer having a surface which was exposed to methylsilane to inhibit an ability of the surface to associate with oxygen;

a dielectric over said substrate; and

a second conductive layer over said first conductive layer.

2. The semiconductor device of claim 1 , wherein:

said dielectric is formed on the first conductive layer; and

said second conductive layer is over said dielectric.

3. The semiconductor device of claim 1 , wherein said first conductive layer is over said dielectric.

4. The semiconductor device of claim 3 , further comprising a third conductive layer between said substrate and said dielectric.

5. A capacitor, comprising:

a bottom plate comprising tungsten nitride and having a surface with a reduced ability to associate with oxygen through exposure of the surface to methylsilane;

a dielectric comprising tantalum pentoxide over said surface; and

a top plate over said dielectric.

6. The capacitor of claim 5 wherein the top plate comprises a polysilicon layer.

7. The capacitor of claim 6 further comprising a BPSG layer formed on the polysilicon layer.

8. A capacitor, comprising:

a first plate having a surface, the surface having been exposed to methylsilane to inhibit an ability of the surface to associate with oxygen;

a dielectric over said first plate; and

a second plate over said dielectric, the second plate comprising:

a first non-polysilicon conductive layer over said dielectric, and

a second conductive layer over said first non-polysilicon conductive layer.

9. The capacitor of claim 8 wherein the first plate comprises a tungsten nitride layer.

10. The capacitor of claim 8 wherein the second conductive layer of the second plate comprises a polysilicon layer.

11. The capacitor of claim 8 wherein the a first non-polysilicon conductive layer of the second plate comprises a tungsten nitride layer.

12. A semiconductor device, comprising:

a conductive line;

a plug adjacent said conductive line; and

an interposing layer between said conductive line and said plug, the interposing layer having a surface exposed to methylsilane to inhibit an ability of the surface to associate with oxygen.

13. The semiconductor device in claim 12 , wherein said interposing layer comprises tungsten nitride.

14. The semiconductor device of claim 12 wherein the conductive line comprises copper.

15. The semiconductor device of claim 12 wherein the plug comprises at least one of polysilicon, tungsten, copper, or aluminum.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2016
From: MICRON TECHNOLOGY, INC.
To: APTINA IMAGING CORPORATION
Reel/Frame 040275/0970 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2016
From: AGARWAL, VISHNU K.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040261/0907 →