IP Library › Assignment 040275/0970
Patent Assignment
Reel/Frame 040275/0970

Assignment of Assignor's Interest

Recorded: 2016-11-10 Pages: 20
Assignor
MICRON TECHNOLOGY, INC.
Executed: 2008-09-26
Assignee
APTINA IMAGING CORPORATION
C/O CITICO TRUSTEES (CAYMAN) LIMITED, REGATTA OFFICE PARK, WEST BAY ROAD, GRAND CAYMAN, Y1-1205, CAYMAN ISLANDS
Covered Properties (36)
Leads Under Chip in Conventional Ic Package
Patent: 6,271,580 →
Application: 09/301,710 →
Leads Under Chip in Conventional Ic Package
Patent: 6,277,673 →
Application: 09/302,083 →
Leads Under Chip Ic Package
Patent: 6,130,474 →
Application: 09/417,159 →
Semiconductor Wafer Assemblies
Patent: 6,320,246 →
Application: 09/556,244 →
Method of Forming a Conductive Contact on a Substrate and Method of Processing a Semiconductor Substrate Using an Ozone Treatment
Patent: 6,602,785 →
Application: 09/614,361 →
Etching methods
Patent: 6,344,364 →
Application: 09/645,057 →
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 7,041,550 →
Application: 09/652,579 →
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 6,852,622 →
Application: 09/652,580 →
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 6,489,194 →
Application: 09/652,581 →
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 6,479,340 →
Application: 09/652,582 →
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 6,607,975 →
Application: 09/652,583 →
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 6,808,976 →
Application: 09/652,714 →
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 6,720,215 →
Application: 09/652,840 →
Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 7,094,657 →
Application: 09/652,841 →
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 6,916,699 →
Application: 09/652,842 →
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 6,468,854 →
Application: 09/652,920 →
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 6,924,188 →
Application: 09/652,968 →
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 7,049,191 →
Application: 09/652,993 →
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 7,067,861 →
Application: 09/652,994 →
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 6,472,264 →
Application: 09/653,121 →
Conductive Material for Integrated Circuit Fabrication
Patent: 6,518,181 →
Application: 09/815,949 →
Publication: US 2001/0042868
Conductive Material for Integrated Circuit Fabrication
Patent: 6,646,456 →
Application: 09/815,964 →
Publication: US 2001/0030552
Leads Under Chip in Conventional Ic Package
Patent: 6,445,061 →
Application: 09/852,868 →
Publication: US 2001/0031553
Method and Apparatus for Endpointing a Chemical-Mechanical Planarization Process
Patent: 6,562,182 →
Application: 09/909,579 →
Publication: US 2002/0019067
Method and Apparatus for Endpointing a Chemical-Mechanical Planarization Process
Patent: 6,517,668 →
Application: 09/910,356 →
Publication: US 2001/0042596
Method and Apparatus for Endpointing a Chemical-Mechanical Planarization Process
Patent: 6,776,871 →
Application: 09/910,661 →
Publication: US 2002/0014310
Methods for Leads Under Chip in Conventional Ic Package
Patent: 6,830,961 →
Application: 09/918,739 →
Publication: US 2001/0045629
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 6,897,512 →
Application: 09/981,764 →
Publication: US 2002/0025694
Method of Forming a Metal Seed Layer for Subsequent Plating
Patent: 6,756,301 →
Application: 10/285,552 →
Publication: US 2003/0054632
Leads Under Chip Ic Package
Patent: 6,958,528 →
Application: 10/300,300 →
Publication: US 2003/0067059
Conductive Material for Integrated Circuit Fabrication
Patent: 6,781,365 →
Application: 10/428,434 →
Publication: US 2003/0183949
Conductive Material for Integrated Circuit Fabrication
Patent: 6,765,398 →
Application: 10/428,703 →
Publication: US 2003/0183521
Conductive Material for Integrated Circuit Fabrication
Patent: 6,870,380 →
Application: 10/428,968 →
Publication: US 2003/0206035
Device and Method for Protecting Against Oxidation of a Conductive Layer in Said Device
Patent: 6,972,452 →
Application: 10/805,118 →
Publication: US 2004/0175898
Conductive Material for Integrated Circuit Fabrication
Patent: 7,046,029 →
Application: 11/108,603 →
Publication: US 2005/0225340
Leads Under Chip Ic Package
Patent: 7,084,490 →
Application: 11/185,346 →
Publication: US 2005/0248006
Related Assignments (6)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Nov 8, 2016
From: CORISIS, DAVID J.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040256/0506 →
Assignment of Assignor's Interest Nov 8, 2016
From: AGARWAL, VISHNU K.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040256/0608 →
Assignment of Assignor's Interest Nov 8, 2016
From: HU, YONGJUN JEFF
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040257/0570 →
Assignment of Assignor's Interest Nov 9, 2016
From: AGARWAL, VISHNU K.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040261/0907 →
Assignment of Assignor's Interest Nov 9, 2016
From: SHARAN, SUJIT; SANDHU, GURTEJ S.; GILTON, TERRY
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040264/0129 →
Assignment of Assignor's Interest Nov 15, 2016
From: GILTON, TERRY
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040329/0033 →