Sequential read-out method and system that employs a single amplifier for multiple columns
View Patent ↗Sequential read-out method and system for reading out an array of photocells are disclosed. The array includes a plurality of photocells that are arranged in rows and columns. A sequential readout circuit is provided for reading out the values of each photocells in a sequential fashion. The sequential readout circuit processes one photocell at a time and can, for example, determine a difference between a final integration light value and a reset value for each photocell in a time sequential manner.
1. A sequential read-out circuit comprising:
a first sample and hold circuit that includes a first sampling switch and a first sampling capacitor, the first sampling capacitor having a first and a second electrode;
a first photocell in an array of photocells, the first photocell comprising a first read switch and a first photodiode, the first read switch being operable to couple the first photodiode to the first electrode of the first sampling capacitor; and
an amplifier having a positive input terminal coupled to a reference voltage, the amplifier configured for operation in one of a unity gain mode and a charge transfer mode, wherein when operating in the unity gain mode, the first sampling switch is operable to couple the second electrode of the first sampling capacitor to a negative input terminal of the amplifier, thereby placing the second electrode of the first sampling capacitor at a voltage level equal to the reference voltage;
a second sample and hold circuit that includes a second sampling switch and a second sampling capacitor, the second sampling capacitor having a first and a second electrode;
a second photocell in an array of photocells, the second photocell comprising a second read switch and a second photodiode, the second read switch being operable to couple the second photodiode to the first electrode of the second sampling capacitor; and
wherein the first sampling switch is operable to uncouple the second electrode of the first sampling capacitor from the negative input terminal of the amplifier and the second sampling switch is operable to couple the second electrode of the second sampling capacitor to the negative input terminal of the amplifier, thereby placing the second electrode of the second sampling capacitor at the reference voltage.
2. The sequential read-out circuit of claim 1 , further comprising a first integration capacitor coupled between the negative input terminal of the amplifier and an output terminal of the amplifier whereby the amplifier is configured when placed in the charge transfer mode of operation, to provide a first voltage gain that is referenced to the voltage reference.
3. The sequential read-out circuit of claim 2 , further comprising a first switching element having a first electrode coupled to the first integration capacitor and a second electrode coupled to the output terminal of the amplifier, the first switching element being operable to selectively couple the first integration capacitor to the output terminal of the amplifier.
4. The sequential read-out of claim 3 , further comprising a second switching element having a first electrode coupled to a shift voltage and a second electrode coupled to the output terminal of the amplifier, the second switching element being operable to set the output terminal of the amplifier at the shift voltage.
5. The sequential read-out circuit of claim 2 , further comprising a second integration capacitor selectively coupled between the negative input terminal of the amplifier and the output terminal of the amplifier whereby the amplifier is configured when placed in the charge transfer mode of operation, to provide a second voltage gain that is referenced to the reference voltage.
6. The sequential read-out circuit of claim 5 , further comprising a third switching element having a first electrode coupled to the second integration capacitor and a second electrode coupled to the output terminal of the amplifier, the third switching element being operable to selectively couple the second integration capacitor to the output terminal of the amplifier.
7. The sequential read-out circuit of claim 1 wherein the amplifier is selectively coupled (a) between the negative input terminal of the amplifier and the second electrode of the first sampling capacitor, and (b) between the negative input terminal of the amplifier and the second electrode of the second sampling capacitor.
8. The sequential read-out circuit of claim 1 wherein, when operated in the unity gain mode, the first electrode of the first sampling capacitor is coupled to a voltage V light generated by the first photodiode and the second electrode of the first sampling capacitor is placed at the reference voltage; and when operated in the charge transfer mode, the amplifier provides a first output voltage constituting a read-out of the first photodiode.
9. The sequential read-out circuit of claim 8 , further comprising:
a second sample and hold circuit comprising a second sampling capacitor; and wherein when operated in the charge transfer mode, the amplifier provides a second output voltage constituting a read-out of the second photodiode.