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App. No. 10/003,237 · Confirmation No. 4498

METHOD OF DESIGNING HIERARCHICAL LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND COMPUTER PRODUCT

Inventor: Nobuyuki Ikeda
Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362 View Patent ↗ View Publication ↗
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2003-11-04 IFEE Issue Fee Payment (PTO-85B) 1 View
2003-11-04 A.NA Amendment after Notice of Allowance (Rule 312) 1 View
2003-11-04 CLM Claims 3 View
2003-11-04 REM Applicant Arguments/Remarks Made in an Amendment 1 View
2001-12-06 TRNA Transmittal of New Application 2 View
2001-12-06 ADS Application Data Sheet 3 View
2001-12-06 A.PE Preliminary Amendment 14 View
2001-12-06 SPEC Specification 19 View
2001-12-06 CLM Claims 5 View
2001-12-06 ABST Abstract 1 View
2001-12-06 DRW Drawings-only black and white line drawings 5 View
2001-12-06 OATH Oath or Declaration filed 3 View
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Quick Facts
App. No.
10/003,237
Filed
2001-12-06
Granted
2003-12-30
Pub. No.
US20030014719A1
Examiner
LIN, SUN J
Art Unit
2851
PTA
0 days