Microcomputer and dividing circuit
View Patent ↗Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
1. A CPU comprising:
an instruction register coupled to a memory;
a plurality of general purpose registers, including a first register, a second register and a third register, and
a program counter which has an address of instruction to be fetched from the memory to the instruction register,
wherein the memory stores a plurality of instructions to be processed by said CPU, the instructions including a conditional branch instruction, an unconditional branch instruction and an add instruction, the add instruction for executing to add contents of the first register to contents of the second register and to place results of the addition in the third register.
wherein the instruction register receives an arbitrary one of the conditional branch instruction, the unconditional branch instruction, the add instruction or other instructions from the memory,
wherein an instruction bit length of the conditional branch instruction is the same as those of the unconditional branch instruction and the add instruction, and
wherein a bit length of a displacement of the conditional branch instruction is different from a bit length of a displacement length of the unconditional branch instruction, and
wherein a value of the displacement is added to the address of the program counter, and a result of the addition is stored in the program counter.
2. The CPU according to claim 1 , wherein the CPU is formed on a semiconductor chip.
3. The CPU according to claim 2 , wherein the displacement length of the conditional branch instruction is smaller than that of the unconditional branch instruction.
4. The CPU according to claim 3 , wherein each of the instruction bit lengths of the conditional branch instruction, the unconditional branch instruction and the add instruction is 16 bits.
5. A CPU comprising:
an instruction register receiving an instruction to be processed by said CPU, sequentially:
a plurality of general purpose registers including a first register, a second register and a third register; and
a program counter which has first contents representing an address of an instruction to be fetched and stored to said instruction register,
wherein said instructions include a conditional branch instruction, an unconditional branch instruction and an add instruction, said add instruction for executing to add content of said first register to content of said second register and to place a result of the addition into said third register,
wherein said instruction register is capable of receiving any of said conditional branch instruction, said unconditional branch instruction, said add instruction, or other instructions,
wherein each of said conditional branch instruction, said unconditional branch instruction and said add instruction has the same instruction bit length,
wherein a bit length of a displacement of said conditional branch instruction is smaller than a bit length of a displacement of said unconditional branch instruction,
wherein said displacement indicates second contents, and
wherein said second contents is added to said first contents, and a result of addition is stored in said program counter.