Switched-capacitor controller to control the rise times of on-chip generated high voltages
View Patent ↗A switched capacitor controller accurately controls the rise time of an on-chip generated high voltage. An on-chip charge pump is used to generate a high voltage (VPP) from an external power supply voltage (VCC). This high voltage signal (VPP) can be used to program Flash memory cells. A capacitor of a switched capacitor circuit is selectively switched between ground and a given node voltage. This generates a stair-stepped ramp function. The period of the steps is controlled according to a clock signal. This clock signal may be altered to produce the desired period. The voltage increases of the steps is regulated by a reference voltage multiplied by a ratio between two capacitor values. Thereby, the rise-time of the ramp function is accurately controlled as a function of the frequency of the clock signal and the ratio of the two capacitor values.
1. A circuit for controlling the rise time of a signal, comprising:
a voltage multiplication circuit for converting an input voltage corresponding to said signal to an output voltage greater than said input voltage;
a ramp generator coupled to said voltage multiplication circuit for controlling said output voltage from said voltage multiplication circuit, wherein a ratio between a first capacitor of said ramp generator and a second capacitor of said ramp generator determines said rise time of said signal, wherein said signal comprises a staircase ramp signal;
a divide by N counter coupled to said ramp generator for generating a plurality of clock phases wherein said ramp generator is controlled with said clock phases; and
a keeper device coupled to said voltage multiplication circuit for allowing said voltage multiplication circuit to selectively hold said signal at a supply voltage and, upon enabling, to perform said converting.
2. The circuit of claim 1 , wherein said voltage multiplication circuit comprises a charge pump.
3. The circuit of claim 1 , wherein said signal is used to program and erase Flash EPROM cells.
4. The circuit of claim 1 further comprising a level shifter.
5. The circuit of claim 1 further comprising two non-overlapping clock signals.
6. The circuit of claim 1 further comprising a ring oscillator coupled to said ramp generator.
7. The circuit of claim 1 further comprising a capacitor divider network coupled to a switched capacitor network.
8. The circuit of claim 7 , wherein said switched capacitor network switches between ground potential and potential of a node of said capacitor divider network.
9. The circuit of claim 8 , wherein said node is coupled to a CMOS comparator.
10. A switched capacitor controller for controlling a rise time of an on-chip generated voltage source, comprising:
a charge pump for converting an input voltage corresponding to said signal to an output voltage greater than said input voltage;
a ramp generator coupled to said charge pump, wherein said ramp generator comprises a switched capacitor network;
a regulator circuit coupled to said switched capacitor network circuit which causes a capacitor to switch between ground potential and the potential at a node, wherein a stair-step ramp signal is generated and said rise time is controlled with said switched capacitor, wherein said switched capacitor network comprises two capacitors wherein said rise time is controlled according to a ratio of capacitances of said two capacitors;
an oscillator coupled to said charge pump which generates an oscillating signal to said charge pump; and
a keeper device coupled to said charge pump for selectively allowing said charge pump to hold said signal at a supply voltage and, upon enabling, to perform said converting.
11. The switched capacitor controller of claim 10 further comprising:
a divider coupled to said oscillator;
a non-overlapping two phase clock generator coupled to said divider.
12. The switched capacitor controller of claim 10 , wherein said ramp generator further comprises a capacitor divider network.
13. In a flash memory, a method for controlling a rise time of an on-chip generated voltage source used to program said flash memory, comprising:
generating a programming voltage VPP for programming a cell of flash memory from a power supply via a ring oscillator, wherein said programming voltage is selectively greater than a supply voltage VCC from said power supply upon enabling and held to said supply voltage VCC without said enabling;
activating a program control signal PGM to enable programming of said cell of said flash memory;
generating a stair-case ramp corresponding to said programming voltage VPP in response to said program control signal PGM, wherein steps of said stair-case ramp have a period corresponding to a clock signal generated by a clock generator and voltage increases corresponding to a reference voltage times a ratio of two capacitor values.
14. The method of claim 13 further comprising switching a capacitor between ground potential and the potential at a node to generate said stair-case ramp.