Semiconductor integrated circuit device
View Patent ↗A semiconductor integrated circuit device is provided in which (i) inspection pads are arranged along one side or two opposite sides of the semiconductor integrated circuit device for bonding pads arranged along the sides other than the side or the two opposite sides and (ii) the bonding pads are connected to their respective inspection pads by connection wires The inspection is carried out by applying probe needles to the pads (inspection pads and bonding pads) arranged only along one side or two opposite sides of the semiconductor integrated circuit device. The invention also provides a semiconductor integrated circuit package with leads on four sides includes a semiconductor integrated circuit device with bonding pads laid along one pair of opposite sides of the four sides, and a table for supporting the semiconductor integrated circuit device. While the bonding pads along the pair of opposite sides of the semiconductor integrated circuit device are connected with leads along the four sides of the package, and some leads are bent toward the respective pads. The present invention the inspection of a plurality of semiconductor integrated circuit devices with probe needles at a time.
1. A semiconductor integrated circuit device comprising:
a semiconductor chip embedded in the semiconductor integrated circuit device, the semiconductor chip comprising:
a first bonding pad arranged on a first side of the semiconductor chip;
a second bonding pad arranged on a second side of the semiconductor chip;
a first input and output buffer and a second input and output buffer which are coupled to the first and second bonding pads respectively;
a first inspection pad;
a first connecting wire which is laid outside an area where the first and second input and output buffers are arranged and which connects the second bonding pad to the first inspection pad;
a plurality of other first bonding pads arranged on the first side of the semiconductor chip;
a plurality of other second bonding pads arranged on the second side of the semiconductor chip;
a plurality of other first connection wires; and
a plurality of other first inspection pads arranged on the first side of the semiconductor chip, each of the plurality of the inspection pads connected to the corresponding second bonding pads,
wherein the first inspection pad is arranged on the first side of the semiconductor chip, and
wherein each of the plurality of the first connection wires has an identical length.
2. A semiconductor integrated circuit device comprising:
a semiconductor chip embedded in the semiconductor integrated circuit device, the semiconductor chip comprising:
a first bonding pad arranged on a first side of the semiconductor chip;
a second bonding pad arranged on a second side of the semiconductor chip;
a first input and output buffer and a second input and output buffer which are coupled to the first and second bonding pads respectively;
a first inspection pad;
a first connecting wire which is laid outside an area where the first and second input and output buffers are arranged and which connects the second bonding pad to the first inspection pad;
a third bonding pad arranged on a third side of the semiconductor chip, the third side facing the first side;
a fourth bonding pad arranged on the second side of the semiconductor chip;
a third input and output buffer and a fourth input and output buffer which are coupled to the third and fourth bonding pads respectively;
a second inspection pad; and
a second connection wire which is laid outside an area where the third and fourth input and output buffers are arranged and which connects the fourth bonding pad to the second inspection pad,
wherein the first inspection pad is arranged on the first side of the semiconductor chip and only connected to one bonding pad on the second side of the semiconductor chip such that the second bonding pad on the second side and the first bonding pad on the first side are set to be tested concurrently through respectively probing the first inspection pad and the first bonding pad on the first side, and
wherein the second inspection pad is arranged on the third side of the semiconductor chip and only connected to one bonding pad on the second side of the semiconductor chip such that the fourth bonding pad on the second side and the third bonding pad on the third side are set to be tested concurrently through respectively probing the second inspection pad and the third bonding pad on the third side.