Methods, apparatus, and systems for reducing interference on nearby conductors
View Patent ↗In a method of data transmission according to one embodiment of the invention, data transitions having the same clock dependence are separated in space. In one such method, signals of one set are transmitted on corresponding conductive paths in one direction, signals of another set are transmitted on corresponding conductive paths in the other direction, and adjacent conductive paths that each carry a signal of one set are separated by at least one conductive path that carries a signal of another set. In an apparatus according to one embodiment of the invention, the conductive paths are fabricated on a semiconductor substrate.
1. A system for data transmission, said system comprising:
a plurality of conductive paths;
a first transmitter configured and arranged to receive a plurality of first input signals, each having a series of state transitions, and to transmit a corresponding plurality of first output signals, each having a series of state transitions corresponding to the series of state transitions of the corresponding first input signal; and
a second transmitter configured and arranged to receive a plurality of second input signals, each having a series of state transitions, and to transmit a corresponding plurality of second output signals, each having a series of state transitions corresponding to the series of state transitions of the corresponding second input signal,
wherein a first of two ends of each one among the plurality of conductive paths is closer to the first end of an adjacent conductive path than to the second end of the adjacent conductive path, and
wherein the first transmitter is further configured and arranged to apply each first output signal to the first end of the corresponding conductive path, and
wherein the second transmitter is further configured and arranged to apply each second output signal to the second end of the corresponding conductive path, and
wherein adjacent conductive paths carrying first output signals are separated by at least one conductive path carrying a second output signal.
2. The system for data transmission according to claim 1 , wherein each state transition of an output signal corresponds to a different one among the state transitions of the corresponding input signal.
3. The system for data transmission according to claim 1 , wherein the conductive paths are parallel to one another.
4. The system for data transmission according to claim 1 , wherein the first and second transmitters are fabricated on the same semiconductor substrate.
5. The system for data transmission according to claim 4 , wherein a length of each of the conductive paths is at least five centimeters.
6. The system for data transmission according to claim 1 , wherein a distance between a pair of the conductive paths is less than one hundred microns.
7. The system for data transmission according to claim 1 , wherein a width of each of the conductive paths is less than one hundred microns.
8. The system for data transmission according to claim 1 , wherein each of the first and second transmitters is further configured and arranged to receive an operating voltage from two power rails, and
wherein the two power rails are parallel to and on opposite sides of the plurality of conductive paths.
9. The system for data transmission according to claim 1 , wherein each one among the plurality of conductive paths includes a corresponding one of a plurality of parallel transmission lines, and
wherein the state transitions of each among the plurality of first output signals are synchronous to a clock signal, and
wherein the first transmitter is further configured and arranged to couple the clock signal to one of the plurality of parallel transmission lines.
10. The system for data transmission according to claim 1 , wherein each among the plurality of conductive paths includes a corresponding one of a plurality of buffers.
11. The system for data transmission according to claim 1 , wherein the state transitions of each among the plurality of first input signals and of each among the plurality of second input signals are synchronized to a data clock signal, and
wherein the state transitions of each among the plurality of first output signals are synchronous to one among the rising and falling edges of a clock signal based on the data clock signal, and
wherein the state transitions of each among the plurality of second output signals are synchronous to the other among the rising and falling edges of the clock signal based on the data clock signal.