Granted Patent
Utility
US 6,555,416
· Confirmation No. 4095
CHIP SIZE PACKAGE SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-12-21 | TRNA |
Transmittal of New Application | 2 | View | |
| 2001-12-21 | A.PE |
Preliminary Amendment | 6 | View | |
| 2001-12-21 | SPEC |
Specification | 20 | View | |
| 2001-12-21 | CLM |
Claims | 4 | View | |
| 2001-12-21 | ABST |
Abstract | 1 | View | |
| 2001-12-21 | DRW |
Drawings-only black and white line drawings | 21 | View | |
| 2001-12-21 | OATH |
Oath or Declaration filed | 1 | View |
Inventors
Hirofumi Nakamura
Tokyo, JAPAN
Masamoto Tago
Tokyo, JAPAN
Attorneys & Agents of Record
Classification
USPC
438/108
H10W74/129
H10D62/117
H10W72/07251
H10W72/536
H10W74/15
H10W72/552
H10W72/20
H10W74/00
H10W90/724
H10W72/5522
H10W90/734
H10W70/60
H10W70/656
Prosecution
- Examiner
- GEYER, SCOTT B
- Art Unit
- 2829
- Docket No.
- Q67764
- Confirmation No.
- 4095
Foreign Priority
09-271323
·
1997-10-03
·
JAPAN
Publication
- Pub. No.
- US20020068383A1
- Pub. Date
- 2002-06-06
Patent Term Adjustment
0days
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Quick Facts
- Patent No.
- US 6,555,416
- App. No.
- 10/023,805
- Filed
- 2001-12-21
- Granted
- 2003-04-29
- Pub. No.
- US20020068383A1
- Examiner
- GEYER, SCOTT B
- Art Unit
- 2829
- PTA
- 0 days
External Links