High speed add-compare-select operations for use in viterbi decoders
View Patent ↗Techniques are provided for the addition and comparison operations associated with a Viterbi decoding algorithm at substantially the same time. To this end, an operation of the type a±b>c±d (where a and b are to be added, c and d are to be added, and then the sums compared to determine the larger of the two sums) can be formulated, in accordance with the invention, into a±b−c∓d>0 (where the addition of a and b and of c and d, and their comparison, are substantially concurrently performed). More specifically, in order to facilitate substantially concurrent addition and comparison operations in a Viterbi decoder, in one embodiment, the present invention performs multi-operand addition in a carry save form. With the results of addition represented in carry save form, the evaluation of comparator conditions is relatively straightforward.
1. A method of performing add-compare-select operations in accordance with a Viterbi decoder, the method comprising the steps of:
respectively adding input values of two or more sets of input values to generate sums for the two or more sets;
substantially concurrent with the respective addition of the input values of the two or more sets of input values, comparing the two or more sets of input values, wherein the comparison operation comprises performing carry save addition on the two sets of input values, and evaluating a carry output of the carry save addition operation to make the determination as to which set of the two or more sets would yield a particular result; and
selecting one of the generated sums of the two or more input sets based on the comparison operation performed on the two or more sets of input values.
2. The method of claim 1 , wherein the comparison operation further comprises comparing the two or more sets of input values to make a determination as to which set of the two or more sets would result in the largest sum.
3. The method of claim 1 , wherein the carry save addition operation is performed by one or more data compressors.
4. The method of claim 1 , wherein one input value of each set of input values is a previously computed path metric and the other input value of each set of input values is an appropriate branch metric such that the generated sum of the input values represents a new path metric which may potentially be selected based on the substantially concurrent comparison operation.
5. The method of claim 1 , wherein the comparison operation begins when the input values of the two or more sets are available such that the comparison operation is completed before completion of the addition operation.
6. Apparatus for performing add-compare-select operations in accordance with a Viterbi decoder, the apparatus comprising:
at least one processor operative to: (i) respectively add input values of two or more sets of input values to generate sums for the two or more sets; (ii) substantially concurrent with the respective addition of the input values of the two or more sets of input values, compare the two or more sets of input values, wherein the comparison operation comprises performing carry save addition on the two sets of input values, and evaluating a carry output of the carry save addition operation to make the determination as to which set of the two or more sets would yield a particular result; and (iii) select one of the generated sums of the two or more input sets based on the comparison operation performed on the two or more sets of input values; and
a memory, coupled to the at least one processor, for storing at least a portion of results associated with one or more of the add, compare, select operations.
7. The apparatus of claim 6 , wherein the comparison operation further comprises comparing the two or more sets of input values to make a determination as to which set of the two or more sets would result in the largest sum.
8. The apparatus of claim 6 , wherein one input value of each set of input values is a previously computed path metric and the other input value of each set of input values is an appropriate branch metric such that the generated sum of the input values represents a new path metric which may potentially be selected based on the substantially concurrent comparison operation.
9. The apparatus of claim 6 , wherein the comparison operation begins when the input values of the two or more sets are available such that the comparison operation is completed before completion of the addition operation.
10. A Viterbi decoder for performing an add-compare-select algorithm, the algorithm comprising the steps of:
respectively adding input values of two or more sets of input values to generate sums for the two or more sets;
substantially concurrent with the respective addition of the input values of the two or more sets of input values, comparing the two or more sets of input values, wherein the comparison operation comprises performing carry save addition on the two sets of input values, and evaluating a carry output of the carry save addition operation to make the determination as to which set of the two or more sets would yield a particular result; and
selecting one of the generated sums of the two or more input sets based on the comparison operation performed on the two or more sets of input values.
11. The Viterbi decoder of claim 10 , wherein the comparison operation further comprises comparing the two or more sets of input values to make a determination as to which set of the two or more sets would result in the largest sum.
12. The Viterbi decoder of claim 10 , wherein the Viterbi decoder comprises an integrated circuit device.
13. An article of manufacture for performing add-compare-select operations in accordance with a Viterbi decoder, the article comprising a machine readable medium containing one or more programs which when executed implement the steps of:
respectively adding input values of two or more sets of input values to generate sums for the two or more sets;
substantially concurrent with the respective addition of the input values of the two or more sets of input values, comparing the two or more sets of input values, wherein the comparison operation comprises performing carry save addition on the two sets of input values, and evaluating a carry output of the carry save addition operation to make the determination as to which set of the two or more sets would yield a particular result; and
selecting one of the generated sums of the two or more input sets based on the comparison operation performed on the two or more sets of input values.
14. The article of claim 13 , wherein the comparison operation further comprises comparing the two or more sets of input values to make a determination as to which set of the two or more sets would result in the largest sum.
15. An integrated circuit device, the integrated circuit device comprising a Viterbi decoder operable to:
respectively add input values of two or more sets of input values to generate sums for the two or more sets;
substantially concurrent with the respective addition of the input values of the two or more sets of input values, compare the two or more sets of input values, wherein the comparison operation comprises performing carry save addition on the two sets of input values, and evaluating a carry output of the carry save addition operation to make the determination as to which set of the two or more sets would yield a particular result; and
select one of the generated sums of the two or more input sets based on the comparison operation performed on the two or more sets of input values.
16. The integrated circuit device of claim 15 , wherein the comparison operation further comprises comparing the two or more sets of input values to make a determination as to which set of the two or more sets would result in the largest sum.