Method and system for forming dual gate structures in a nonvolatile memory using a protective layer
View Patent ↗A method and system for providing a semiconductor device is described. The semiconductor includes a core and a periphery. The method and system include providing a plurality of core gate stacks in the core, a plurality of sources in the core and a plurality of periphery gate stacks in the periphery. Each of the plurality of core gate stacks includes a first polysilicon gate and a WSi layer above the first polysilicon gate. The plurality of sources resides between a portion of the plurality of core gate stacks. Each of the plurality of periphery gate stacks includes a second polysilicon gate and a CoSi layer on the second polysilicon gate.
1. A semiconductor device including a core and a periphery, the semiconductor device comprising:
a plurality of core gate stacks in the core, each of the plurality of core gate stacks including a first polysilicon gate and a WSi layer above the first polysilicon gate, wherein each of the plurality of core gate stacks includes an edge;
a plurality of core spacers, each of the plurality of core spacers residing along an edge of the plurality core gate stacks;
a plurality of sources in the core, the plurality of sources residing between a portion of the plurality of core gate stacks; and
a plurality of periphery gates stacks in the periphery, each of the plurality of periphery gate stacks including a second polysilicon gate and a CoSi layer on the second polysilicon gate;
wherein each of the plurality of core gate stacks includes the first polysilicon gate, the WSi layer above the first polysilicon gate, a layer of polysilicon above the WSi later and a capping layer above the layer of polysilicon.
2. The semiconductor device of claim 1 wherein the capping layer is a SiN layer.
3. The semiconductor device of claim 1 wherein the capping layer is a SiON layer.
4. A semiconductor device comprising:
a plurality of core gate stacks in a core, wherein each of said plurality of core gate stacks comprises a first polysilicon gate and a WSi layer above said first polysilicon gate and a polysilicon capping layer above said WSi layer and an additional capping layer above said polysilicon capping layer;
a plurality of sources in said core, wherein said plurality of sources resides between a portion of said plurality of core gate stacks; and
a plurality of periphery gate stacks in a periphery, wherein each of said plurality of periphery gate stacks comprises a second polysilicon gate and a CoSi layer above said second polysilicon gate.
5. The semiconductor device as recited in claim 4 wherein said additional capping layer functions as an antireflective layer.
6. The semiconductor device as recited in claim 4 wherein said additional capping layer is a SiN layer.
7. The semiconductor device as recited in claim 4 , wherein said additional capping layer is a SiON layer.