IP Library Granted Patent US 6,911,682
Granted Patent B2
US 6,911,682 · App. 10/033,323 · Granted Jun 28, 2005

Electromechanical three-trace junction devices

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Quick Facts
Patent No.
US 6,911,682
App. No.
10/033,323
Granted
Jun 28, 2005
Kind
B2
Abstract

Three trace electromechanical circuits and methods of using same are described. A circuit includes first and second electrically conductive elements with a nanotube ribbon (or other electromechanical elements) disposed therebetween. The nanotube ribbon is movable toward at least one of the first and second electrically conductive elements in response to electrical stimulus applied to at least one of the first and second electrically conductive elements and the nanotube ribbon. Such circuits may be formed into arrays of cells. The upper and lower electrically conductive traces may be aligned or unaligned vertically. An electrical stimulus may be applied to at least one of the first and second electrically conductive elements and the nanotube ribbon to move the nanotube ribbon toward at least one of the first and second electrically conductive elements. Electrical signals from at least one the first and second electrically conductive elements and the nanotube ribbon may be sensed to determine the electrical state of the cell. The states may be assigned in a variety of ways. For example, if the ribbon is moved toward the first electrically conductive element, the electrical state is a first state; if the ribbon is moved toward the second electrically conductive element, the electrical state is a second state; and if the ribbon is between the first and second electrically conductive elements, the electrical state is a third state. The first, second, and third states each corresponds to a different information encoding. Or, electrical stimulus may be applied to both the first and second electrically conductive elements so that the first and second electrically conductive elements both cause the movement of the nanotube ribbon. Or, the first and second electrically conductive elements are used in a fault tolerant manner.

Claims (59)

1. A circuit, comprising

a first electrically conductive element;

a second electrically conductive element; and

a nanotube ribbon disposed between the first and second electrically conductive elements, wherein the nanotube ribbon is movable toward at least one of the first and second electrically conductive elements in response to electrical stimulus applied to at least one of the first and second electrically conductive elements and the nanotube ribbon.

2. The circuit of claim 1 , wherein the first and second electrically conductive elements and the nanotube ribbon each has a longitudinal axis and wherein the longitudinal axis of the nanotube ribbon is oriented to cross logitudinal axes of the first and second electrically conductive elements.

3. The circuit of claim 2 , wherein the longitudinal axes of the first and second electrically conductive elements are parallel.

4. The circuit of claim 3 , wherein the longitudinal axis of the nanotube ribbon is oriented at substantially right angles to the longitudinal axes of the first and second electrically conductive elements.

5. The circuit of claim 1 , wherein the electrically conductive elements are doped silicon traces.

6. The circuit of claim 1 , wherein the nanotube ribbon is of a non-woven fabric of nanotubes.

7. The circuit element of claim 1 , wherein the nanotube ribbon is substantially a monolayer of nanotubes.

8. A circuit array, comprising

a lower structure having a plurality of lower electrically conductive elements and a plurality of lower support structures;

an upper structure having a plurality of upper electrically conductive elements and a plurality of upper support structures; and

a plurality of nanotube ribbons disposed between the lower and upper structures and in contact with the lower support structures and the upper support structures, each nanotube ribbon having a longitudinal orientation that crosses the longitudinal orientation of the plurality of lower and upper electrically conductive elements, and wherein each location where a nanotube ribbon crosses an electrically conductive element defines a circuit cell, and wherein a nanotube ribbon is movable within a circuit cell in response to electrical stimulus applied to at least one of the electrically conductive elements and the nanotube ribbons.

9. The circuit array of claim 8 wherein the upper support structures are vertically aligned with the lower support structure.

10. The circuit array of claim 8 wherein the upper electrically conductive elements are vertically aligned with the lower electrically conductive elements.

11. The circuit array of claim 8 wherein the upper electrically conductive elements are vertically unaligned with the lower electrically conductive elements.

12. The circuit array of claim 8 wherein the lower electrically conductive elements are disposed between the lower support structures and wherein the upper electrically conductive elements have at least a portion of their widths disposed over upper support structures and at least a different portion of their widths protruding past the upper support structures.

13. The circuit array of claim 8 wherein the upper electrically conductive elements and the lower electrically conductive elements are substantially parallel and wherein the nanotube ribbons are arranged substantially perpendicularly to the upper and lower electrically conductive elements.

14. The circuit array of claim 12 , wherein protruding edges of the upper electrically conductive traces extend over corresponding lower electrically conductive elements for about one half the width thereof.

15. The circuit array of claim 8 , wherein the upper and lower electrically conductive elements have about the same width and length.

16. The circuit array of claim 8 , wherein the upper support structures are made of insulating material.

17. The circuit array of claim 8 , wherein the lower support structures are made of insulating material.

18. The circuit array of claim 8 wherein the lower support structures are rows of insulating material protruding from a major surface of the lower structure.

19. The circuit array of claim 8 wherein the lower support structures are columns of insulating material protruding from a major surface of the lower structure.

20. The circuit array of claim 8 wherein the upper support structures are rows of insulating material protruding from a major surface of the upper structure.

21. The circuit array of claim 8 wherein the upper support structures are columns of insulating material protruding from a major surface of the upper structure.

22. The circuit array of claim 8 wherein the lower electrically conductive elements contact adjacent lower support structures.

23. The circuit array of claim 8 wherein the upper electrically conductive elements contact adjacent upper support structures.

24. The circuit array of claim 8 wherein the lower electrically conductive elements are separated from adjacent lower support structures.

25. The circuit array of claim 8 wherein the upper electrically conductive elements are separated from adjacent upper support structures.

26. The circuit array of claim 8 wherein the upper structure includes a gate dielectric layer.

27. The circuit array of claim 8 wherein the lower structure includes a gate dielectric layer.

28. The circuit array of claim 8 wherein the upper electrically conductive elements are made of doped silicon.

29. The circuit array of claim 8 wherein the lower electrically conductive elements are made of doped silicon.

30. The circuit array of claim 8 wherein the upper support structures are made of spin-on glass.

31. The circuit array of claim 8 wherein the lower support structures are made of spin-on glass.

32. The circuit array of claim 8 wherein the upper support structures are made of silicon nitride.

33. The circuit array of claim 8 wherein the lower support structures are made of silicon nitride.

34. The circuit array of claim 8 wherein the upper support structures are made of polyimide.

35. The circuit array of claim 8 wherein the upper electrically conductive elements are made of low melting point metal.

36. A circuit, comprising

a first electrically conductive element;

a second electrically conductive element; and

an electromechanically responsive element disposed between the first and second electrically conductive elements, wherein the nanotube ribbon is movable toward at least one of the first and second electrically conductive elements in response to electrical stimulus applied to at least one of the first and second electrically conductive elements and the nanotube ribbon.

37. The circuit of claim 36 wherein the electromechanically responsive element is a nanotube.

38. A circuit array, comprising

a lower structure having a plurality of lower electrically conductive elements and a plurality of lower support structures;

an upper structure having a plurality of upper electrically conductive elements and a plurality of upper support structures; and

a plurality of electromechanically responsive elements disposed between the lower and upper structures and in contact with the lower support structures and the upper support structures, each electromechanically responsive element having a longitudinal orientation that crosses the longitudinal orientation of the plurality of lower and upper electrically conductive elements, and wherein each location where an electromechanically responsive element crosses an electrically conductive element defines a circuit cell, and wherein an electromechanically responsive element is movable within a circuit cell in response to electrical stimulus applied to at least one of the electrically conductive elements and the electromechanically responsive elements.

39. The circuit array of claim 38 wherein the electromechanically responsive elements are nanotubes.

40. A method of using a circuit cell having a first electrically conductive element, a second electrically conductive element, and a nanotube ribbon disposed between the first and second electrically conductive elements, comprising:

applying electrical stimulus to at least one of the first and second electrically conductive elements and the nanotube ribbon to move the nanotube ribbon toward at least one of the first and second electrically conductive elements;

sensing electrical signals from at least one the first and second electrically conductive elements and the nanotube ribbon to determine the electrical state of the cell.

41. The method of claim 40 wherein, if the ribbon is moved toward the first electrically conductive element, the electrical state is a first state; if the ribbon is moved toward the second electrically conductive element, the electrical state is a second state; and if the ribbon is between the first and second electrically conductive elements, the electrical state is a third state, in which each of the first, second, and third states corresponds to a different information encoding.

42. The method of claim 40 wherein electrical stimulus is applied to both the first and second electrically conductive elements so that the first and second electrically conductive elements both cause the movement of the nanotube ribbon.

43. The method of claim 40 wherein the first and second electrically conductive elements are used in a fault tolerant manner.

44. The method of claim 40 , wherein the electrical stimulus is applied to cause the nanotube ribbon to move to a position in electrical contact with one of the first and second electrically conductive elements.

45. The method of claim 40 , wherein the circuit cell is used as a base-2 memory cell.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2021
From: SILICON VALLEY BANK
To: NANTERO, INC.
Reel/Frame 056790/0001 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Nov 11, 2020
From: NANTERO, INC.
To: SILICON VALLEY BANK
Reel/Frame 054383/0632 →
LICENSE Recorded Aug 20, 2008
From: NANTERO, INC.
To: LOCKHEED MARTIN CORPORATION
Reel/Frame 021411/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2005
From: BROCK, DARREN K.
To: NANTERO, INC.
Reel/Frame 016609/0140 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2001
From: RUECKES, THOMAS; SEGAL, BRENT M.; BROCK, DARREN K.
To: NANTERO, INC.
Reel/Frame 012423/0562 →