System and method for DC offset compensation and bit synchronization
View Patent ↗A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D converter connected to the radio module, a DC tracking loop connected to the A/D converter, and a multi-hypothesis bit synchronizer.
1. A method for operating a wireless device, the method comprising:
receiving a data signal;
accumulating a first sample sum value for a first set of DC compensated samples of the received data signal, the first set of DC compensated samples corresponding to a first timing hypothesis;
accumulating a second sample sum for a second set of DC compensated samples of the received data signal, the second set of DC compensated samples corresponding to a second timing hypothesis;
accumulating a third sample sum value for a third set of DC compensated samples of the received data signal, the third set of DC compensated samples corresponding to a third timing hypothesis;
computing a first averaged sample sum using the first sample sum;
computing a second averaged sample sum using the second sample sum;
computing a third averaged sample sum using the third sample sum;
identifying the maximum of the first averaged sample sum, the second averaged sample sum, and the third averaged sample sum; and
generating an output symbol corresponding to the identified maximum.
2. The method of claim 1 wherein the output symbol is of a first value when the sample sum corresponding to the identified maximum is positive and is otherwise of a second value.
3. The method of claim 1 ,
wherein the first sample sum value is defined as
SS
E
(
k
)
=
∑
i
=
k
-
(
N
+
1
)
k
-
2
y
(
i
)
and wherein the second sample sum is defined as
S
S
O
(
k
)
=
∑
i
=
k
-
n
k
-
1
y
(
i
)
and wherein the third sample sum is defined as
S
S
L
(
k
)
=
∑
i
=
k
-
(
N
-
1
)
k
y
(
i
)
.
and wherein k an integer representing a sample time index and N is an integer representing a multiple of a symbol rate.
4. The method of claim 3 ,
wherein the first averaged sample sum is defined as
Ē ( k )=( E ( k )>>β)+ Ē ( k− 1)−( Ē ( k− 1)>>β)
in which >> is a bit shift operation and in which β is a parameter used to control integration time,
and wherein the second averaged sample sum is defined as
Ō ( k )=( O ( k )>>β)+ Ō ( k− 1)−( Ō ( k− 1)>>β)
and wherein the third averaged sample sum is defined as
L ( k )=( L ( k )>>β)+ L ( k− 1)−( L ( k− 1)>>β)
wherein
E ( k )=| SS E ( k )|
O ( k )=| SS O ( k )|
L ( k )=| SS L ( k )|.
5. The method of claim 1 , further comprising:
responsive to the identified maximum corresponding to the third sample sum, adjusting a symbol timing.
6. The method of claim 5 , wherein a standard next symbol time is plus n samples, the method further comprising:
adjusting the next symbol timing to be plus n+1 samples.
7. The method of claim 1 , further comprising:
computing a DC offset estimate;
wherein the accumulation of the first sample sum, the second sample sum, and the third sample sum accounts for the computed DC offset estimate.
8. The method of claim 7 , further comprising:
subtracting the DC offset estimate from a first set of samples to thereby generate the first set of DC compensated samples.
9. The method of claim 8 , further comprising:
receiving the DC offset estimate from an initial offset calculator.
10. The method of claim 9 , further comprising:
calculating the DC offset estimate using a pilot signal.
11. The method of claim 1 , wherein the first set of DC compensated samples and the second set of DC compensated samples are offset by one sample.
12. An electronic device comprising:
a DC offset compensator;
a plurality of sample accumulators, each of the plurality of sample accumulators being coupled with the DC offset compensator; and
a maximum identifier coupled with each of the plurality of sample accumulators;
wherein the maximum identifier is configured to identify the maximum output of the plurality of sample accumulators and cause an output to be generated according to the identified maximum output.
13. The electronic device of claim 12 , wherein the plurality of sample accumulators includes an on-time accumulator, the electronic device further comprising:
a symbol clock control coupled with the maximum identifier;
wherein the symbol clock control is configured to adjust a symbol timing responsive to the maximum identifier identifying the maximum output to be from one of the plurality of sample accumulators other than the on-time accumulator.
14. The electronic device of claim 12 , further comprising:
a DC tracking loop coupled with the DC offset compensator;
wherein the DC tracking loop is configured to provide a DC estimate to the DC offset compensator.
15. The electronic device of claim 12 , wherein the electronic device is a cellular phone.
16. The electronic device of claim 12 , wherein the electronic device is a personal digital assistant.
17. The electronic device of claim 12 , wherein the electronic device is a peripheral device.
18. The electronic device of claim 12 , wherein the plurality of accumulators comprises:
an early accumulator;
an on-time accumulator; and
a late accumulator.
19. An apparatus comprising:
means for receiving a data signal;
means for accumulating a first sample sum for a first set of samples of the received data signal, the first set of samples corresponding to a first timing hypothesis;
means for accumulating a second sample sum for a second set of samples of the received data signal, the second set of samples corresponding to a second timing hypothesis;
means for accumulating a third sample sum for a third set of samples of the received data signal, the third set of samples corresponding to a third timing hypothesis;
means for computing a first averaged sample sum using the first sample sum;
means for computing a second averaged sample sum using the second sample sum;
means for computing a third averaged sample sum using the third sample sum;
means for identifying the maximum of the first averaged sample sum, the second averaged sample sum, and the third averaged sample sum; and
means for outputting a symbol corresponding to the identified maximum;
wherein the output symbol is a first value when the sample sum corresponding to the identified maximum is positive.
20. The apparatus of claim 19 , further comprising:
means for adjusting symbol timing responsive to the identified maximum corresponding to the third sample sum.
21. The apparatus of claim 20 , wherein a standard next symbol time is plus n samples, the apparatus further comprising:
means for adjusting the next symbol timing to be plus n+1 samples.
22. The apparatus of claim 19 , further comprising:
means for compensating for a DC offset;
wherein the means for accumulating the first sample sum, the second sample sum, and the third sample sum accounts for the computed DC offset.
23. The apparatus of claim 19 , wherein the means for compensating for the DC offset comprises:
means for subtracting a DC offset estimate from the first set of samples.
24. The apparatus claim 23 , further comprising:
means for receiving the DC offset estimate from an initial offset calculator.
25. The apparatus of claim 23 , further comprising:
means for calculating the DC offset estimate using a pilot signal.