Design for test of analog module systems
View Patent ↗An apparatus for testing an integrated circuit that includes analog nodes is disclosed. In one aspect, an integrated circuit comprises testing circuitry and core logic circuitry. A memory in the testing circuitry stores data identifying analog nodes in the core logic circuitry and tolerance values associated with the analog nodes. A condition checker compares actual test values with the associated tolerance values. A main control unit controls the testing circuitry and synchronizes testing of the core logic circuitry. In another aspect, the testing circuitry includes a host computer interface useful for communicating with a host computer. A data memory in the testing circuitry is used for storing diagnostic data. The contents of the data memory may then be uploaded to a host computer. Test stimuli may be transmitted to the integrated circuit from a location outside the integrated circuit to perform testing.
1. A method for testing an integrated circuit having multiple analog nodes and testing circuitry, comprising:
selecting an analog node in the integrated circuit from a list of analog nodes stored in a memory;
obtaining a test value from the selected analog node;
retrieving a tolerance value associated with the selected analog node from a memory; and
comparing the test value of the selected analog node with the tolerance value, wherein the comparing is performed by a condition checker in the testing circuitry, the condition checker performing comparisons of test values and tolerance values for plural analog nodes in the integrated circuit.
2. The method of claim 1 wherein the associated tolerance value is retrieved from the same memory in which the list of analog nodes is stored.
3. The method of claim 1 , wherein the comparing comprises checking whether the test value of the selected analog node is within the associated tolerance value.
4. The method of claim 3 further comprising generating an error indication signal in response to the checking.
5. The method of claim 4 further comprising: reconfiguring a memory in the integrated circuit to be operable to store diagnostic data from the testing circuitry.
6. The method of claim 5 further comprising:
storing data identifying the selected analog node in the memory; and
storing the test value of the selected analog circuit in the memory.
7. The method of claim 4 further comprising:
storing data identifying the selected analog node in a data memory in the testing circuitry; and
storing the test value of the selected analog node in a data memory in the testing circuitry.
8. The method of claim 7 wherein the data identifying the selected analog node and the test value of the selected analog circuit are stored in the same data memory.
9. The method of claim 8 further comprising:
obtaining a test value of a second analog node, wherein the second analog node is associated with the selected analog node;
storing data identifying the second analog node in the data memory; and
storing the test value of the second analog node in the data memory.
10. The method of claim 8 further comprising uploading the contents of the data memory to a host computer.
11. The method of claim 1 wherein the obtaining is responsive to stimuli transmitted to the integrated circuit from a location outside the integrated circuit.
12. The method of claim 1 further comprising:
prior to the comparing, selecting a condition checker in the testing circuitry for performing the comparing.
13. The method of claim 1 further comprising, prior to the selecting:
storing data identifying the analog nodes of the integrated circuit in a program memory in the testing circuitry;
storing tolerance values associated with the analog nodes of the integrated circuit in the program memory.