Patent Assignment
Reel/Frame 057279/0707
Merger and Change of Name
Recorded: 2021-06-16
Pages: 7
Assignors
MENTOR GRAPHICS CORPORATION
Executed: 2020-12-30
SIEMENS INDUSTRY SOFTWARE INC.
Executed: 2020-12-30
Assignee
SIEMENS INDUSTRY SOFTWARE INC.
5800 GRANITE PARKWAY, SUITE 600, PLANO, TEXAS, 75024
Covered Properties
(99)
Spatial Characteristic and Logical Hierarchy Based Manner for Compactly Storing Ic Design Data and Related Operations
Patent:
6,539,519 →
Application:
09/585,719 →
Accessing State Information in a Hardware/Software Co-Simulation
Patent:
7,072,820 →
Application:
09/587,496 →
Integrated Verification and Manufacturability Tool
Patent:
6,425,113 →
Application:
09/593,923 →
Method and Apparatus for Testing High Performance Circuits
Patent:
6,510,534 →
Application:
09/607,128 →
Integrated Circuit Design Correction Using Fragment Correspondence
Patent:
6,516,459 →
Application:
09/613,213 →
Convergence Technique for Model-Based Optical and Process Correction
Patent:
6,430,737 →
Application:
09/613,214 →
Hierarchical Design and Test Method and System, Program Product Embodying the Method and Integrated Circuit Produced Thereby
Patent:
6,615,392 →
Application:
09/626,877 →
Method and Apparatus for Creating Photolithographic Masks
Patent:
6,728,946 →
Application:
09/703,294 →
Conversion of an Hdl Sequential Truth Table to Generic Hdl Elements
Patent:
6,874,134 →
Application:
09/731,535 →
Authenticating Communications
Wiring Harness Data Systems
Patent:
7,107,197 →
Application:
09/771,115 →
Method for Scan Testing of Digital Circuit, Digital Circuit for Use Therewith and Program Product for Incorporating Test Methodology into Circuit Description
Data Management Method for Mask Writing
Method and Program Product for Modeling Circuits with Latch Based Design
Method and Program Product for Detecting Bus Conflict and Floating Bus Conditions in Circuit Designs
Circuit for Switching Between Multiple Clocks
Patent:
6,452,426 →
Application:
09/836,700 →
Prioritizing the Application of Resolution Enhancement Techniques
Method and Apparatus for Improving Resolution of Objects in a Semiconductor Wafer
Emulator with Switching Network Connections
Method and Circuit for Testing High Frequency Mixed Signal Circuits with Frequency Signals
Method of Designing Circuit Having Multiple Test Access Ports, Circuit Produced Thereby and Method of Using Same
Short Edge Management in Rule Based Opc
Patent:
6,574,784 →
Application:
09/882,802 →
Coherent State Among Multiple Simulation Models in an Eda Simulation Environment
Patent:
7,401,015 →
Application:
09/883,836 →
Synchronization of Multiple Simulation Domains in an Eda Simulation Environment
Method of Routing Traces on a Virtual Circuit Board
Patent:
7,516,544 →
Application:
09/888,173 →
Circuit and Method for Detecting Transient Voltages on a Dc Power Supply Rail
Method of Testing Embedded Memory Array and Embedded Memory Controller for Use Therewith
Debugger for a Hardware-Implemented Operating System
Cross Function Block Partitioning and Placement of a Circuit Design Onto Reconfigurable Logic Devices
Space Classification for Resolution Enhancement Techniques
Flexible Horizontal Stack Display and Editor
Method,System and Program Product for Testing and/or Diagnosing Circuits Using Embedded Test Controller Access Data
Emulation Components and System Including Distributed Event Monitoring, and Testing of an Ic Design Under Emulation
Emulation Components and System Including Distributed Routing and Configuration of Emulation Resources
Method and Program Product for Designing Hierarchical Circuit for Quiescent Current Testing and Circuit Produced Thereby
Method and Program Product for Designing Hierarchical Circuit for Quiescent Current Testing
Circuit Synthesis Method Using Technology Parameters Extracting Circuit
Patent:
6,567,971 →
Application:
10/021,810 →
Design for Test of Analog Module Systems
Determining a Minimum Size of Presentation Data
Method and Apparatus to Generate a Wiring Harness Layout
Selective Promotion for Resolution Enhancement Techniques
Intelligent Milling Path Creation for Panelization Abstract
Functional Verification of Logic and Memory Circuits with Multiple Asynchronous Domains
Patent:
6,817,001 →
Application:
10/103,617 →
Mechanism to Organize Windows in a Graphic Application
Patent:
7,269,797 →
Application:
10/113,553 →
Memory Device
Method and Circuitry for Controlling Clocks of Embedded Blocks During Logic Bist Test Mode
Test Access Circuit and Method of Accessing Embedded Test Controllers in Integrated Circuit Modules
Method for Collecting Failure Information for a Memory Using an Embedded Test Controller
Method of Masking Corrupt Bits During Signature Analysis and Circuit for Use Therewith
Measure of Analysis Performed in Property Checking
Patent:
6,848,088 →
Application:
10/174,379 →
Scan Test Method for Providing Real Time Identification of Failing Test Patterns and Test Bist Controller for Use Therewith
Hierarchical Feature Extraction for Electrical Interaction Calculations
Performance of Integrated Circuit Components via a Multiple Exposure Technique
Caching of Lithography and Etch Simulation Results
Uniform Testing of Tristate Nets in Logic Bist
Chromeless Phase Mask Layout Generation
Short Edge Smoothing for Enhanced Scatter Bar Placement
Testing the Interrupt Priority Levels in a Microprocessor
Repartitioning Performance Estimation in a Hardware-Software System
Automated Repartitioning of Hardware and Software Components in an Embedded System
Automating Interactions with Software User Interfaces
Graphical Calculator with Hierarchical View of Usage History
Selection of Initial States for Formal Verification
Patent:
7,454,324 →
Application:
10/340,500 →
Verification of Embedded Test Structures in Circuit Designs
Hierarchical Evaluation of Cells
Circuit and Method for Adding Parametric Test Capability to Digital Boundary Scan
Method of and Program Product for Performing Gate-Level Diagnosis of Failing Vectors
Compression of Emulation Trace Data
Clustering Circuit Paths in Electronic Circuit Design
Representing Device Layout Using Tree Structure
Generating a Split Power Plane of a Multi-Layer Printed Circuit Board
Circuit and Method for Accurately Applying a Voltage to a Node of an Integrated Circuit
Method and Test Circuit for Testing Memory Internal Write Enable
Testing of Reconfigurable Logic and Interconnect Sources
Message-Based Low Latency Circuit Emulation Signal Transfer
Method and Circuit for Collecting Memory Failure Information
Site Control for Opc
Boundary Scan with Strobed Pad Driver Enable
Synchronized Communication Between Integrated Circuit Chips
Mask Creation with Hierarchy Management Using Cover Cells
Method and Circuit for at-Speed Testing of Scan Circuits
Tester Channel Count Reduction Using Observe Logic and Pattern Generator
Ternary Bit Line Signaling
Logic Design Modeling and Interconnection
Nonvolatile Semiconductor Memory Device Providing Stable Data Reading
Metastability Injector for a Circuit Description
Patent:
7,243,322 →
Application:
10/859,055 →
Opc Conflict Identification and Edge Priority System
Method and Apparatus for the Analysis and Optimization of Variability in Nanometer Technologies
Patent:
7,092,838 →
Application:
10/860,812 →
Method and Apparatus for Optimization of Digital Integrated Circuits Using Detection of Bottlenecks
Patent:
7,191,417 →
Application:
10/860,813 →
Compiling Memory Dereferencing Instructions from Software to Hardware in an Electronic Design
Distributed Electronic Design Automation Environment
Modelling and Simulation Method
Circuit and Method for Measuring Jitter of High Speed Signals
In-Line Xor Checking of Master Cells During Integrated Circuit Design Rule Checking
Method and System for Hardware Accelerated Verification of Digital Circuit Design and Its Testbench
Logic Injection
Clock Controller for at-Speed Testing of Scan Circuits
Selectively Reducing the Number of Cell Evaluations in a Hardware Simulation
Compilation of Remote Procedure Calls Between a Timed Hdl Model on a Reconfigurable Hardware Platform and an Untimed Model on a Sequential Computing Platform
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.