Message-based low latency circuit emulation signal transfer
View Patent ↗Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.
1. A reconfigurable emulation integrated circuit, comprising:
a storage unit comprising a signal inclusion schedule; and
circuitry, coupled to the storage unit, operative to generate and transmit a message outside the reconfigurable emulation integrated circuit, the message assembled in accordance with the signal inclusion schedule and comprising a plurality of emulation signals, wherein the signal inclusion schedule selects the plurality of emulation signals from at least one pin when the message is assembled and specifies the order and frequency of occurrence of each of the plurality of emulation signals in the message.
2. The reconfigurable emulation integrated circuit of claim 1 , wherein the frequency of occurrence specified by the signal inclusion schedule is based on a determination that particular emulation signals in the message are more critical than other emulation signals in the message, and the particular emulation signals that are more critical occur in the message with greater frequency than the other emulation signals in the message.
3. The reconfigurable emulation integrated circuit of claim 2 , wherein the order specified by the signal inclusion schedule is determined based on the determined frequency of occurrence.
4. The reconfigurable emulation integrated circuit of claim 1 , wherein the message is generated and transmitted in a plurality of clock cycles of an operating clock that is independent of an emulation clock of the plurality of signals.
5. The reconfigurable emulation integrated circuit of claim 1 , wherein the circuitry further includes a parity value generator and wherein the message further comprises a parity value generated by the parity value generator.
6. The reconfigurable emulation integrated circuit of claim 1 , wherein the message is generated and transmitted for a number of clock cycles of an operating clock, and the signal inclusion schedule is determined to provide a number of signal selections equal to the number of clock cycles.
7. The reconfigurable emulation integrated circuit of claim 1 , wherein the message is generated and transmitted for a number of clock cycles of an operating clock, and the signal inclusion schedule is determined to provide a number of signal selections less than the number of clock cycles.
8. A reconfigurable integrated circuit, comprising:
a storage unit comprising a signal inclusion schedule for a plurality of emulation signals to be received in a message, the plurality of emulation signals selected from at least one pin when the message is assembled; and
circuitry, coupled to the storage unit, operative to receive the message and extract the plurality of emulation signals from the message in accordance with the signal inclusion schedule, wherein the signal inclusion schedule specifies the order and frequency of occurrence of each of the plurality of emulation signals in the message.
9. The reconfigurable emulation integrated circuit of claim 8 , wherein the frequency of occurrence specified by the signal inclusion schedule is based on a determination that particular emulation signals in the message are more critical than other emulation signals in the message, and the particular emulation signals that are more critical occur in the message with greater frequency than the other emulation signals in the message.
10. The reconfigurable emulation integrated circuit of claim 8 , wherein the message comprises state values of the plurality of emulation signals.
11. The reconfigurable emulation integrated circuit of claim 8 , wherein the message is received and disassembled in a plurality of clock cycles of an operating clock that is independent of an emulation clock of the plurality of emulation signals.
12. The reconfigurable emulation integrated circuit of claim 8 , wherein a parity value is extracted from the message.
13. The reconfigurable emulation integrated circuit of claim 12 , wherein the circuitry is further configured to generate a parity verification value from the extracted plurality of emulation signals and compare the parity verification value with the extracted parity value.
14. An emulation integrated circuit, comprising:
at least one reconfigurable logic resource;
at least one output pin; and
a message formation and send block in communication with the output pin and the reconfigurable logic resource, the message formation and send block operative to receive emulation signals from the reconfigurable logic resource and generate a message on the output pin in accordance with a first signal inclusion schedule that selects at least one of the emulation signals when the message is generated, wherein the first signal inclusion schedule specifies the order and frequency of occurrence of each of the emulation signals in the message.
15. The emulation integrated circuit of claim 14 , further comprising:
an input pin; and
a message receive and disassembly block in communication with the input pin and the reconfigurable logic resource, operative to receive a message and extract second emulation signals from the message in accordance with a second signal inclusion schedule.
16. The emulation integrated circuit of claim 14 , further comprising a second output pin and a second message formation and send block in communication with the second output pin and the reconfigurable logic resource, the second message formation and send block operative to receive emulation signals from the reconfigurable logic resource and generate a second message on the output pin in accordance with a different signal inclusion schedule.
17. The emulation integrated circuit of claim 14 , further comprising a plurality of reconfigurable logic resources in communication with the message formation and send block.
18. An emulation integrated circuit, comprising:
at least one reconfigurable logic resource;
at least one input pin; and
a message receive and disassembly block in communication with the reconfigurable logic resource and the input pin, the message receive and disassembly block operative to receive a message assembled from a selection of emulation signals from at least one pin when the message is assembled in accordance with a first signal inclusion schedule, wherein the message is received at the at least one input pin and the emulation signals are extracted for the at least one reconfigurable logic resource in accordance with a second signal inclusion schedule, wherein the second signal inclusion schedule specifies the order and frequency of occurrence of each of the emulation signals in the message.
19. The emulation integrated circuit of claim 18 , wherein the first signal inclusion schedule and the second signal inclusion schedule are different signal inclusion schedules.
20. The emulation circuit of claim 18 , wherein the first signal inclusion schedule comprises a message send schedule and the second signal inclusion schedule comprises a message receive schedule.