IP Library Granted Patent US 6,973,633
Granted Patent B2
US 6,973,633 · App. 10/206,691 · Granted Dec 6, 2005

Caching of lithography and etch simulation results

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Quick Facts
Patent No.
US 6,973,633
App. No.
10/206,691
Granted
Dec 6, 2005
Kind
B2
Abstract

One or more control points are identified within a reticle layout that is used in a simulation of a manufacturing process for an integrated device layer. Further, a current geometrical layout pattern is determined in the vicinity of the control points, and a cache is searched for a matching geometrical layout pattern. If the search is successful, a simulation result associated with the matching geometrical layout pattern is retrieved from the cache and reused for the current geometrical layout pattern. Alternatively, if the search is unsuccessful, a simulation result associated with the current geometrical design pattern is computed and stored in the cache for future reuse.

Claims (25)

1. A method of preparing data in a layout for the creation of an integrated device layer, comprising:

identifying one or more control points within a layout used in a simulation of a manufacturing process for the integrated device layer;

determining a geometrical layout pattern corresponding to the one or more control points;

searching a cache for previously computed simulation data associated with the geometric layout pattern; and

retrieving the previously computed simulation data associated with the geometrical layout pattern from the cache for reuse when performing optical and process correction (OPC) on the one or more control points in the layout.

2. The method of claim 1 further comprising:

determining that the cache does not store the simulation data associated with the geometrical layout pattern;

calculating simulation data that is associated with the geometrical layout pattern; and

storing the simulation data associated with the geometrical layout pattern in the cache for reuse during OPC of the layout with additional control points that have a corresponding geometrical layout pattern.

3. The method of claim 1 , wherein the cache is any one of a lookup table, a tree data structure, a sparse matrix data structure and a hash table.

4. The method of claim 1 , wherein the geometrical layout pattern is contained inside a support region that is defined around the one or more control points using an optical radius.

5. The method of claim 4 , wherein the simulation data is at least one of an intensity value, an edge placement error, a rotation value, and an edge slope deviation value.

6. The method of claim 1 , wherein the geometrical layout pattern is a portion of geometry contained inside a support region that is defined around the one or more control points using an optical radius.

7. The method of claim 6 , wherein the portion of geometry is at least one of a polygon and a sub-polygon.

8. The method of claim 7 , wherein the sub-polygon is any one of an edge, a trapezoid, a rectangle, and a triangle.

9. The method of claim 6 , wherein the simulation data is a convolution value associated with the portion of geometry.

10. The method of claim 1 , wherein the simulation data associated with the geometrical layout pattern includes a set of coordinates of portions of the geometrical layout pattern, the set of coordinates identifying positions of the portions relative to the one or more control points.

11. The method of claim 1 , wherein the one or more control points represent a group of points; and

the simulation data includes a set of computation values, each of the set of computation values corresponding to a specific point within the group of control points.

12. The method of claim 1 , wherein:

the one or more control points represent a group of control points; and

the simulation data includes a cumulative computation value corresponding to the entire group of control points.

13. A machine-readable medium having stored thereon sequences of instructions that, when executed, cause one or more electronic systems to perform the method of claim 1 .

14. A computer data signal transmitted in a data communications medium shared among a plurality of network devices that encodes a sequence of instructions that, when executed, cause one or more electronic systems to perform the method of claim 1 .

15. A method of preparing data that describes an integrated device layer, comprising: transmitting data that describes an integrated device layer to a computer that performs the method of claim 1 ; and receiving data that describes the integrated device layer from the computer.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Jun 16, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 057279/0707 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2002
From: LIPPINCOTT, GEORGE; COBB, NICK; TODD, ROBERT
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 013144/0268 →