Mask creation with hierarchy management using cover cells

1. A method of preparing a file that describes an integrated circuit layout for use by a mask writing tool that accepts files having a limited hierarchy, comprising:

receiving a layout file that defines cells arranged in a hierarchical graph;

designating a number of cells as cover cells in the hierarchical graph;

expanding the layout file such that only the designated cover cells remain in the hierarchical graph; and

after designating the cover cells, selectively redefining the hierarchy of the hierarchical graph by expanding and/or copying one or more of the remaining cover cells such that the hierarchical graph has a maximum depth that is less than or equal to the hierarchical limit of the mask writing tool.

2. The method of claim 1 , further comprising determining a number of times a cell appears in a layout wherein the cover cells are designated according to the number of times a cell appears in a layout.

3. The method of claim 1 , further comprising determining a memory area required to describe a cell, wherein the cover cells are designated according to the memory required for the cells.

4. The method of claim 1 , further comprising determining a geometric area occupied by each cell, wherein the cover cells are designated according to the geometric area occupied by the cells.

5. The method of claim 1 , wherein the hierarchy of the hierarchical graph is selectively redefined by:

analyzing the remaining cover cells of the hierarchical graph in a topological order; and

for each cover cell, determining a maximum depth of a subgraph that can be referenced by the cover cell and expanding the cover cell if necessary such that the subgraph has a depth that is less than or equal to the allowed maximum depth.

6. The method of claim 5 , wherein the maximum depth allowed for a subgraph is determined by computing the difference between the hierarchical limit of the mask writer and the maximum depth of any placement of the cover cell that doesn't exceed the hierarchical limit.

7. The method of claim 1 , further comprising creating new cover cells in the hierarchical graph from groups of repeated polygons.

8. The method of claim 1 , further comprising creating new cover cells in the hierarchical graph by dividing or modifying an existing cover cell in the layout file.

9. A computer readable media including a sequence of program interactions that cause a computer to perform the method of claim 1 .

10. A file describing a layout of an integrated circuit that is created by the method of claim 1 .

11. A method of selectively redefining the hierarchy of a hierarchical graph to have a depth that is less than or equal to a defined depth limit, comprising:

receiving a hierarchical graph that includes a number of cells, wherein at least one of the cells has a depth that is greater than the defined depth limit;

designating one or more of the cells as cover cells for the hierarchical graph;

redefining the hierarchical graph in terms of the designated cover cells by expanding the nondesignated cells into the designated cover cells; and

analyzing each cover cell in the redefined hierarchical graph to determine if any placement of the cover cell will cause the defined depth limit to be exceeded, and if so, modifying a subgraph of a cell to meet the defined depth limit.

12. The method of claim 11 , wherein the analysis for each cover cell is determined by:

determining if the maximum depth of a cover cell plus the depth of the cover cell's subgraph exceeds the defined depth limit, and if so, expanding the subgraph into the cover cell.

13. A computer readable media including a sequence of program instructions that cause a computer to perform the method of claim 11 .