OPC conflict identification and edge priority system
View Patent ↗An integrated circuit verification system provides an indication of conflicts between an OPC suggested correction and a manufacturing rule. The indication specifies which edges segments are in conflict so that a user may remove the conflict to achieve a better OPC result. In another embodiment of the invention, edge segments are assigned a priority such that the correction of a lower priority edge does not hinder a desired OPC correction of a higher priority edge.
1. An IC verification system, comprising:
a computer system that executes a sequence of programmed instructions that cause the computer to:
receive a layout design file that defines features to be created in at least a portion of an integrated circuit (IC);
perform optical and process correction (OPC) to determine recommended OPC corrections for edge segments of features in the layout design;
determine if the recommended OPC corrections violate one or more manufacturing rules; and
provide an indication where there is a conflict between a first edge segment and a second edge segment in the layout design that prevents the first edge segment from being moved to its recommended OPC correction.
2. The IC verification system of claim 1 wherein the indication of a conflict visually indicates the first edge segment of a feature that cannot be moved to its recommended OPC correction and the second edge segment that is causing the conflict.
3. The IC verification system of claim 1 , wherein the indication specifies an attribute of an edge segment in its OPC corrected position.
4. The IC verification system of claim 3 , wherein the attribute includes an edge position error for an edge segment.
5. The IC verification system of claim 3 , wherein the attribute includes a difference between an OPC correction that does not violate a manufacturing rule and the recommended OPC correction.
6. The IC verification system of claim 1 , wherein the indication of the conflict indicates which manufacturing rule would be violated as a result of the conflict.
7. A method of performing optical and process correction (OPC) by:
receiving a layout design file that defines features to be created in at least a portion of an integrated circuit (IC);
determining a recommended OPC correction for edge segments of features in the layout design; and
providing an indication of a conflict between a first edge segment and a second edge segment in the layout design that prevents the first edge segment from being moved to its recommended OPC correction to avoid violating a manufacturing rule.
8. The method of claim 7 , wherein the indication is provided by visually indicating where the first edge segment of ;a feature cannot be moved to its recommended OPC correction without causing a conflict.
9. The method of claim 8 , wherein the indication indicates the manufacturing rule that is violated as a result of the conflict.
10. A computer readable medium including a sequence of programmed instructions that cause a computer system to perform optical and process correction (OPC) by:
receiving a layout design file that defines features to be created in at least a portion of an integrated circuit (IC);
determining recommended OPC corrections for edge segments of features in the layout design; and
providing an indication of a conflict between a first edge segment and a second edge segment in the layout design that will violate a manufacturing rule if the first edge segment is moved to its recommended OPC correction.