Nonvolatile semiconductor memory device providing stable data reading

1. A nonvolatile semiconductor memory device, comprising:

a first memory cell having a conductive/nonconductive state thereof substantially controlled in response to data stored therein and providing passage of a first current amount in the conductive state;

a first bit line connected to said first memory cell;

a reference cell connected to said first bit line and providing passage of a second current amount smaller than the first current amount, wherein said reference cell includes a plurality of transistors arranged in series, said transistors having a same dimension as a transistor of said first memory cell;

a second bit line;

a second memory cell connected to said second bit line and providing passage of the first current amount; and

a sense amplifier connectable to said first bit line and said second bit line through electrical couplings.

2. The nonvolatile semiconductor memory device as claimed in claim 1 , wherein the second current amount is substantially half the first current amount.

3. The nonvolatile semiconductor memory device as claimed in claim 2 , wherein said reference cell has a gate length that is longer than that of said first memory cell.

4. The nonvolatile semiconductor memory device is claimed in claim 1 , wherein said first memory cell, said second memory cell, and said reference cell are included in a unitary array structure.

5. The nonvolatile semiconductor memory device as claimed in claim 1 , wherein said reference cell includes:

a first reference cell connected to said first bit line; and

a second reference cell connected to said first bit line, wherein one of said first reference cell and said second reference cell is selectively made conductive in response to a word address that selects said first memory cell.

6. A nonvolatile semiconductor memory device, comprising:

a first memory cell having a conductive/nonconductive state thereof substantially controlled in response to data stored therein and providing passage of a first current amount in the conductive state;

a first bit line connected to said first memory cell;

a reference cell connected to said first bit line and providing passage of a second current amount smaller than the first current amount;

a second bit line;

a second memory cell connected to said second bit line and providing passage of the first current amount;

a sense amplifier connectable to said first bit line and said second bit line through electrical couplings; and

transistors that couple said first bit line and said second bit line to a predetermined potential when said sense amplifier is not operating.

7. The nonvolatile semiconductor memory device as claims in claim 6 , wherein said predetermined potential is connected to source nodes of said first memory cell, said second memory cell, and said reference cell.

8. The nonvolatile semiconductor memory device as claimed in claim 6 , wherein the second current amount is substantially half the first current amount.

9. The nonvolatile semiconductor memory device as claimed in claim 8 , wherein said reference cell has a gate length that is longer than that of said first memory cell.

10. The nonvolatile semiconductor memory device is claimed in claim 6 , wherein said first memory cell, said second memory cell, and said reference cell are included in a unitary array structure.

11. The nonvolatile semiconductor memory device as claimed in claim 6 , wherein said reference cell includes:

a first reference cell connected to said first bit line; and

a second reference cell connected to said first bit line, wherein one of said first reference cell and said second reference cell is selectively made conductive in response to a word address that selects said first memory cell.

12. A nonvolatile semiconductor memory device, comprising:

a memory cell having a conductive/nonconductive state thereof substantially controlled in response to data stored therein and providing passage of a first current amount in the conductive state;

a first bit line connected to said memory cell;

a second bit line;

a reference cell connected to said second bit line and providing passage of a second current amount smaller than the first current amount;

a sense amplifier connectable to said first bit line and said second bit line through electrical couplings; and

transistors configured to couple said first bit line and said second bit line to a predetermined potential when said sense amplifier is not operating.

13. The nonvolatile semiconductor memory device as claimed in claim 12 , wherein said memory cell and said reference cell are included in a unitary array structure.

14. The nonvolatile semiconductor memory device as claim in claim 12 , wherein the second current amount is substantially half the first current amount.

15. A nonvolatile semiconductor memory device, comprising:

a first memory cell having a conductive/nonconductive state thereof substantially controlled in response to data stored therein and providing passage of a first current amount in the conductive state;

a first bit line connected to said first memory cell;

a first reference cell connected to said first bit line and providing, in a conductive state, passage of a second current amount smaller than the first current amount;

a second bit line;

a second memory cell connected to said second bit line and providing passage of the first current amount in a conductive state;

a second reference cell connected to said second bit line and providing passage of the second current amount in a conductive state, wherein said first reference cell and said second memory cell are fixedly set to a conductive state, and said second reference cell is fixedly set to a nonconductive state; and

a sense amplifier connectable to said first bit line and said second bit line through electrical couplings.

16. A nonvolatile semiconductor memory device, comprising:

a first memory cell having a conductive/nonconductive state thereof substantially controlled in response to data stored therein and providing passage of a first current amount in the conductive state;

a first bit line connected to said first memory cell;

a first reference cell connected to said first bit line and providing, in a conductive state, passage of a second current amount smaller than the first current amount;

a second bit line;

a second memory cell connected to said second bit line and providing passage of the first current amount in a conductive state;

a second reference cell connected to said second bit line and providing passage of the second current amount in a conductive state, wherein said first reference cell and said second memory cell are fixedly set to a nonconductive state, and said second reference cell is fixedly set to a conductive state; and

a sense amplifier connectable to said first bit line and said second bit line through electrical couplings.