Granted Patent
Utility
US 6,817,001 · App. 10/103,617
Functional verification of logic and memory circuits with multiple asynchronous domains
Inventors:
Muralidhar R. Kudlugi, Charles W. Selvidge
Patented Case
View Patent ↗
Granted: Nov 9, 2004
Filed: Mar 20, 2002
Inventors
Muralidhar R. Kudlugi
Charles W. Selvidge
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.