Patent Assignment
Reel/Frame 024233/0056
Assignment of Assignor's Interest
Recorded: 2010-04-14
Pages: 9
Assignor
LOGICVISION, INC.
Executed: 2009-09-10
Assignee
MENTOR GRAPHICS CORPORATION
8005 SW BOECKMAN ROAD, WILSONVILLE, OREGON, 97070-7777
Covered Properties
(57)
Multiple Clock Rate Test Apparatus for Testing Digital Systems
Patent:
5,349,587 →
Application:
07/858,377 →
Method and Apparatus for Testing Digital to Analog and Analog to Digital Converters
Patent:
5,659,312 →
Application:
08/663,493 →
Asynchronous Interface
Patent:
5,900,753 →
Application:
08/825,446 →
Method and Apparatus for Testing Multi-Port Memory Using Shadow Read
Patent:
6,046,946 →
Application:
09/047,233 →
Method for Testability Analysis and Test Point Insertion at the Rt-Level of a Hardware Development Language (Hdl) Specification
Patent:
6,363,520 →
Application:
09/098,555 →
Fault Insertion Method, Boundary Scan Cells, and Integrated Circuit for Use Therewith
Patent:
6,536,008 →
Application:
09/181,077 →
Method and Circuit for Built in Self Test of Phase Locked Loops
Patent:
6,396,889 →
Application:
09/184,516 →
Test Circuit and Method for Measuring Switching Point Voltages and Integral Non-Linearity (Inl) of Analog to Digital Converters
Patent:
6,211,803 →
Application:
09/191,154 →
Method and Apparatus for Scan Testing Digital Circuits
Patent:
6,145,105 →
Application:
09/192,839 →
Clock Skew Management Method and Apparatus
Patent:
6,115,827 →
Application:
09/209,790 →
Method and Apparatus for Controlling Power Level During Bist
Patent:
6,330,681 →
Application:
09/218,764 →
Method of Testing at-Speed Circuits Having Asynchronous Clocks and Controller for Use Therewith
Patent:
6,327,684 →
Application:
09/309,827 →
Programmable Clock Signal Generation Circuits and Methods for Generating Accurate, High Frequency, Clock Signals
Patent:
6,204,694 →
Application:
09/316,197 →
Method and Apparatus for Testing Circuits with Multiple Clocks
Patent:
6,442,722 →
Application:
09/430,686 →
Method for Testing Circuits with Tri-State Drivers and Circuit for Use Therewith
Patent:
6,487,688 →
Application:
09/472,386 →
Method and Circuit for Testing Dc Parameters of Circuit Input and Output Nodes
Patent:
6,586,921 →
Application:
09/570,412 →
Method and Apparatus for Testing High Performance Circuits
Patent:
6,510,534 →
Application:
09/607,128 →
Hierarchical Design and Test Method and System, Program Product Embodying the Method and Integrated Circuit Produced Thereby
Patent:
6,615,392 →
Application:
09/626,877 →
Method for Scan Controlled Sequential Sampling of Analog Signals and Circuit for Use Therewith
Method for Scan Testing of Digital Circuit, Digital Circuit for Use Therewith and Program Product for Incorporating Test Methodology into Circuit Description
Method and Program Product for Modeling Circuits with Latch Based Design
Method and Program Product for Detecting Bus Conflict and Floating Bus Conditions in Circuit Designs
Method and Circuit for Testing High Frequency Mixed Signal Circuits with Frequency Signals
Method of Designing Circuit Having Multiple Test Access Ports, Circuit Produced Thereby and Method of Using Same
Circuit and Method for Detecting Transient Voltages on a Dc Power Supply Rail
Method of Testing Embedded Memory Array and Embedded Memory Controller for Use Therewith
Method,System and Program Product for Testing and/or Diagnosing Circuits Using Embedded Test Controller Access Data
Method and Program Product for Designing Hierarchical Circuit for Quiescent Current Testing and Circuit Produced Thereby
Method and Program Product for Designing Hierarchical Circuit for Quiescent Current Testing
Circuit Synthesis Method Using Technology Parameters Extracting Circuit
Patent:
6,567,971 →
Application:
10/021,810 →
Method and Circuitry for Controlling Clocks of Embedded Blocks During Logic Bist Test Mode
Test Access Circuit and Method of Accessing Embedded Test Controllers in Integrated Circuit Modules
Method for Collecting Failure Information for a Memory Using an Embedded Test Controller
Circuit and Method for Determining the Location of Defect in a Circuit
Method of Masking Corrupt Bits During Signature Analysis and Circuit for Use Therewith
Scan Test Method for Providing Real Time Identification of Failing Test Patterns and Test Bist Controller for Use Therewith
Semiconductor Characterization and Production Information System
Patent:
6,720,194 →
Application:
10/262,737 →
Method and Circuit for Testing High Frequency Mixed Signal Circuits with Low Frequency Signals
Method and Program Product for Completing a Circuit Design Having Embedded Test Structures
Self-Contained Embedded Test Design Envoronment and Environment Setup Utility
Verification of Embedded Test Structures in Circuit Designs
Circuit and Method for Adding Parametric Test Capability to Digital Boundary Scan
Method of and Program Product for Performing Gate-Level Diagnosis of Failing Vectors
Circuit and Method for Accurately Applying a Voltage to a Node of an Integrated Circuit
Method and Test Circuit for Testing Memory Internal Write Enable
Method and Circuit for Collecting Memory Failure Information
Boundary Scan with Strobed Pad Driver Enable
Circuit and Method for Testing High Speed Data Circuits
Method and Circuit for at-Speed Testing of Scan Circuits
Memory Repair Analysis Method and Circuit
Memory Repair Circuit and Method
Circuit and Method for Measuring Jitter of High Speed Signals
Circuit and Method for Measuring Delay of High Speed Signals
Clock Controller for at-Speed Testing of Scan Circuits
Clocking Methodology for at-Speed Testing of Scan Circuits with Synchronous Clocks
Method for at-Speed Testing of Memory Interface Using Scan
Method and Apparatus for Storing and Distributing Memory Repair Information
Related Assignments
(4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Oct 28, 2011
From: NORTEL NETWORKS LIMITED
To: ROCKSTAR BIDCO, LP
Reel/Frame 027164/0356 →
Assignment of Assignor's Interest
Oct 29, 2014
From: ROCKSTAR BIDCO, LP
To: ROCKSTAR CONSORTIUM US LP
Reel/Frame 034086/0173 →
Assignment of Assignor's Interest
Feb 9, 2015
From: ROCKSTAR CONSORTIUM US LP; ROCKSTAR CONSORTIUM LLC; BOCKSTAR TECHNOLOGIES LLC; CONSTELLATION TECHNOLOGIES LLC
To: RPX CLEARINGHOUSE LLC
Reel/Frame 034924/0779 →
Merger and Change of Name
Jun 16, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 057279/0707 →