Granted Patent
Utility
US 6,649,487
· Confirmation No. 6775
METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2003-09-17 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2002-01-17 | TRNA |
Transmittal of New Application | 2 | View | |
| 2002-01-17 | A.PE |
Preliminary Amendment | 3 | View | |
| 2002-01-17 | SPEC |
Specification | 48 | View | |
| 2002-01-17 | CLM |
Claims | 7 | View | |
| 2002-01-17 | ABST |
Abstract | 1 | View | |
| 2002-01-17 | DRW |
Drawings-only black and white line drawings | 23 | View | |
| 2002-01-17 | OATH |
Oath or Declaration filed | 2 | View |
Inventors
Attorneys & Agents of Record
Classification
USPC
438/424
H10D84/0109
H10D84/038
H10W10/00
H10W10/041
H10W10/17
H10W10/012
H10W10/0147
H10W10/01
H10W10/13
H10W10/40
Prosecution
- Examiner
- MAI, ANH D
- Art Unit
- 2814
- Customer No.
- 20457
- Docket No.
- 501.33748CC3
- Confirmation No.
- 6775
Foreign Priority
6-120894
·
1994-06-02
·
JAPAN
Publication
- Pub. No.
- US20020102815A1
- Pub. Date
- 2002-08-01
Patent Term Adjustment
0days
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2014-05-13
from
HITACHI, LTD.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2011-03-25
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Quick Facts
- Patent No.
- US 6,649,487
- App. No.
- 10/046,813
- Filed
- 2002-01-17
- Granted
- 2003-11-18
- Pub. No.
- US20020102815A1
- Examiner
- MAI, ANH D
- Art Unit
- 2814
- PTA
- 0 days
External Links