Integrated chip package structure using metal substrate and method of manufacturing the same
View Patent ↗An integrated chip package structure and method of manufacturing the same is by adhering dies on a metal substrate and forming a thin-film circuit layer on top of the dies and the metal substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
1. A method for fabricating a chip package, comprising:
joining a die and a substrate, wherein said die has a top surface at a horizontal level, wherein said die and said substrate are under said horizontal level;
after said joining said die and said substrate, forming a patterned circuit layer over said horizontal level, wherein said patterned circuit layer extends across an edge of said die;
after said joining said die and said substrate, forming a passive device over said substrate and over said horizontal level, wherein said passive device is not vertically over said die;
after said joining said die and said substrate, forming a metal bump over said horizontal level; and
after said forming said patterned circuit layer, said forming said passive device, and said forming said metal bump then, separating said substrate into multiple portions.
2. The method of claim 1 , wherein said substrate comprises a metal substrate.
3. The method of claim 2 , wherein said metal substrate comprises aluminum.
4. The method of claim 2 , wherein said metal substrate comprises copper.
5. The method of claim 1 further comprising joining a film and said substrate, wherein an opening in said film exposes said substrate, followed by said joining said die and said substrate, wherein said die is in said opening.
6. The method of claim 5 , wherein forming said opening in said film comprises a punching process.
7. The method of claim 5 , wherein said film comprises a metal layer.
8. The method of claim 1 , wherein said forming said patterned circuit layer comprises an electroplating process.
9. The method of claim 1 , wherein said forming said patterned circuit layer comprises a sputtering process.
10. The method of claim 1 , wherein said forming said passive device comprises an electroplating process.
11. The method of claim 1 , wherein said forming said passive device comprises a sputtering process.
12. The method of claim 1 , wherein said passive device comprises an inductor.
13. The method of claim 1 , wherein said passive device comprises a capacitor.
14. The method of claim 1 , wherein said passive device comprises a resistor.
15. The method of claim 1 , wherein said passive device comprises a filter.
16. The method of claim 1 , wherein said forming said metal bump comprises forming a solder bump over said horizontal level.
17. The method of claim 1 , wherein said forming said metal bump comprises forming a gold bump over said horizontal level.
18. A method for fabricating a chip package, comprising:
providing a first die having a top surface at a horizontal level, a second die having a top surface at said horizontal level, and a separating material between said first and second dies, wherein said separating material separates said first die from said second die;
after said providing said first and second dies and said separating material, forming a passive device over said horizontal level, wherein said passive device is not vertically over said first and second dies, wherein said passive device has a first terminal connected to said first die; and
after said forming said passive device, forming a metal bump over said horizontal level, wherein said metal bump is connected to a second terminal of said passive device.
19. The method of claim 18 further comprising providing a substrate joining said first and second dies, followed by said forming said passive device further over said substrate.
20. The method of claim 19 , wherein said substrate comprises a metal substrate.
21. The method of claim 19 , after said forming said metal bump, further comprising separating said substrate into multiple portions.
22. The method of claim 18 , wherein said separating material comprises an epoxy.
23. The method of claim 18 , after said providing said first and second dies and said separating material, further comprising forming a patterned circuit layer over said horizontal level and over said separating material, wherein said patterned circuit layer extends across an edge of said first die, followed by said forming said metal bump.
24. The method of claim 23 , wherein said forming said patterned circuit layer comprises an electroplating process.
25. The method of claim 23 , wherein said forming said patterned circuit layer comprises a sputtering process.
26. The method of claim 18 , wherein said forming said passive device comprises an electroplating process.
27. The method of claim 18 , wherein said forming said passive device comprises a sputtering process.
28. The method of claim 18 , wherein said forming said metal bump comprises forming a solder bump over said horizontal level, wherein said solder bump is connected to said second terminal.
29. The method of claim 18 , wherein said forming said metal bump comprises forming a gold bump over said horizontal level, wherein said gold bump is connected to said second terminal.
30. The method of claim 18 , wherein said passive device comprises an inductor.
31. The method of claim 18 , wherein said passive device comprises a capacitor.
32. The method of claim 18 , wherein said passive device comprises a resistor.
33. The method of claim 18 , wherein said passive device comprises a filter.
34. The method of claim 18 , wherein said separating material comprises a polymer.
35. A method for fabricating a chip package, comprising:
providing a first die having a top surface at a horizontal level, a second die having a top surface at said horizontal level, and a separating material between said first and second dies, wherein said separating material separates said first die from said second die;
after said providing said first and second dies and said separating material, forming a passive device over said horizontal level, wherein said passive device is not vertically over said first and second dies;
after said forming said passive device over said horizontal level, forming an insulating layer on said passive device and over said horizontal level;
after said providing said first and second dies and said separating material, forming a patterned circuit layer over said horizontal level, wherein said patterned circuit layer extends across an edge of said first die; and
after said forming said insulating layer and said forming said patterned circuit layer, forming a metal bump over said horizontal level.
36. The method of claim 35 , wherein said forming said patterned circuit layer comprises an electroplating process.
37. The method of claim 35 , wherein said forming said patterned circuit layer comprises a sputtering process.
38. The method of claim 35 , wherein said forming said passive device comprises an electroplating process.
39. The method of claim 35 , wherein said forming said passive device comprises a sputtering process.
40. The method of claim 35 , wherein said passive device comprises an inductor.
41. The method of claim 35 , wherein said passive device comprises a capacitor.
42. The method of claim 35 , wherein said passive device comprises a resistor.
43. The method of claim 35 , wherein said passive device comprises a filter.
44. The method of claim 35 , wherein said separating material comprises an epoxy.
45. The method of claim 35 further comprising providing a substrate joining said first and second dies, followed by said forming said passive device further over said substrate, and said forming said patterned circuit layer further over said substrate.
46. The method of claim 45 , wherein said substrate comprises a metal substrate.
47. The method of claim 45 , after said forming said metal bump, further comprising separating said substrate into multiple portions.
48. The method of claim 35 , wherein said separating material comprises a polymer.
49. The method of claim 35 , wherein said forming said metal bump comprises forming a solder bump over said horizontal level.
50. The method of claim 35 , wherein said forming said metal bump comprises forming a gold bump over said horizontal level.