Patent Assignment
Reel/Frame 017600/0649
Assignment of Assignor's Interest
Recorded: 2006-05-11
Received: 2006-05-11
Pages: 5
Assignor
MEGIC CORPORATION
Executed: 2006-04-28
Assignee
MEGICA CORPORATION
ROOM 301/ 302, NO.47, PARK 2ND RD., SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, TWX, TAIWAN
Covered Properties
(30)
Chip Package with Dam Bar Restricting Flow of Underfill
Application:
11/307,127 →
Circuit Component with Bump Formed Over Chip
Application:
11/123,328 →
Chip Structure and Process for Forming the Same
Application:
11/123,936 →
Process of Bonding Circuitry Components
Application:
11/124,493 →
Chip Structure and Process for Forming the Same
Application:
10/997,145 →
Method for Fabricating Chip Package
Application:
10/977,289 →
Method for Fabricating Circuitry Component
Application:
10/933,961 →
Chip Structure with a Passive Device and Method for Forming the Same
Application:
10/710,596 →
Bonding Structure with Pillar and Cap
Application:
10/874,704 →
Method for Fabricating Circuitry Component
Application:
10/794,472 →
Integrated Chip Package Structure Using Silicon Substrate and Method of Manufacturing the Same
Application:
10/755,042 →
Chip Structure with Pads Having Bumps or Wirebonded Wires Formed Thereover or Used to Be Tested Thereto
Application:
10/730,834 →
Electronic Component with Die and Passive Device
Application:
10/728,150 →
Chip Package with Multiple Chips Connected by Bumps
Application:
10/695,630 →
Process of Fabricating a Chip Structure
Application:
10/690,250 →
Circuitry Component with Metal Layer Over Die and Extending to Place Not Over Die
Application:
10/638,018 →
Method for Fabricating Chip Package with Die and Substrate
Application:
10/454,972 →
Method for Fabricating Circuitry Component
Application:
10/382,699 →
Chip Structure and Process for Forming the Same
Application:
10/337,673 →
Chip Structure and Process for Forming the Same
Application:
10/337,668 →
Integrated Chip Package Structure Using Silicon Substrate and Method of Manufacturing the Same
Application:
10/174,462 →
Method of Fabricating Cylindrical Bonding Structure
Application:
10/174,357 →
Chip Structure and Process for Forming the Same
Application:
10/125,226 →
Chip Structure and Process for Forming the Same
Application:
10/124,388 →
Integrated Chip Package Structure Using Ceramic Substrate and Method of Manufacturing the Same
Application:
10/055,498 →
Semiconductor device with metal pillar
Application:
10/055,580 →
Chip Package with Die and Substrate
Application:
10/055,568 →
Integrated Chip Package Structure Using Organic Substrate and Method of Manufacturing the Same
Application:
10/055,499 →
Integrated Chip Package Structure Using Metal Substrate and Method of Manufacturing the Same
Application:
10/055,560 →
Wide Bit Memory Using Post Passivation Interconnection Scheme
Application:
09/801,327 →