Electronic component with die and passive device
View Patent ↗An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
1. A chip package comprising:
a first die having a top surface at a horizontal level;
a patterned wiring layer over said horizontal level, wherein said patterned wiring layer comprises a first portion across an edge of said die;
a first polymer layer over said horizontal level and on said first die, wherein said first polymer layer is the only one polymer layer between said first die and said patterned wiring layer, and wherein said patterned wiring layer is connected to said first die through an opening in said first polymer layer and is on said first polymer layer;
a passive device over said horizontal level; and
a second polymer layer on said passive device.
2. The chip package in claim 1 further comprising a substrate joined with said first die, wherein said substrate is under said horizontal level.
3. The chip package in claim 2 , wherein said substrate comprises polymer.
4. The chip package in claim 2 , wherein said substrate comprises resin.
5. The chip package in claim 2 , wherein said substrate comprises imide.
6. The chip package in claim 2 , wherein said substrate comprises plastic.
7. The chip package in claim 2 , wherein said substrate comprises thermosetting plastic.
8. The chip package in claim 1 , wherein said first polymer layer comprises polyimide (PI).
9. The chip package in claim 1 , wherein said first polymer layer comprises benzocyclobutene (BCB).
10. The chip package in claim 1 , wherein said first polymer layer comprises a porous structure.
11. The chip package in claim 1 , wherein said second polymer layer comprises polyimide (PI).
12. The chip package in claim 1 , wherein said second polymer layer comprises benzocyclobutene (BCB).
13. The chip package in claim 1 , wherein said second polymer layer comprises a porous structure.
14. The chip package in claim 1 , wherein said top surface comprises multiple pads.
15. The chip package in claim 1 , wherein said patterned wiring layer comprises a second portion connecting multiple internal circuits of said first die.
16. The chip package in claim 15 , wherein said second portion is used to transmit a signal.
17. The chip package in claim 15 , wherein said second portion is used to provide a power voltage.
18. The chip package in claim 15 , wherein said second portion is used to provide a ground voltage.
19. The chip package in claim 1 further comprising a second die having a top surface at said horizontal level, wherein said patterned wiring layer comprises a second portion connecting said first die and said second die.
20. The chip package in claim 1 further comprising a film layer around said first die.
21. The chip package in claim 20 , wherein said film layer comprises polymer.
22. The chip package in claim 20 , wherein said film layer comprises epoxy.
23. The chip package in claim 20 , wherein said film layer has a top surface at said horizontal level.
24. The chip package in claim 1 further comprising a bump over said horizontal level, wherein said bump comprises solder.
25. The chip package in claim 1 further comprising a bump over said horizontal level, wherein said bump comprises gold.
26. The chip package in claim 1 , wherein said passive device comprises a resistor.
27. The chip package in claim 1 , wherein said passive device comprises a capacitor.
28. The chip package in claim 1 , wherein said passive device comprises an inductor.
29. The chip package in claim 1 , wherein said passive device comprises a filter.
30. The chip package in claim 1 , wherein said passive device comprises a waveguide.
31. The chip package in claim 1 , wherein said passive device comprises a micro electronic mechanical sensor (MEMS).
32. The chip package in claim 1 , wherein said passive device is not directly over said first die.
33. The chip package in claim 1 , wherein said passive device is connected to said first die.
34. The chip package in claim 1 , wherein said patterned wiring layer comprises copper.