Circuit component with bump formed over chip
View Patent ↗A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.
1. A chip comprising:
a semiconductor substrate;
a MOS device in or on said semiconductor substrate;
a first metal pad over said semiconductor substrate;
a passivation layer over said semiconductor substrate, wherein an opening in said passivation layer exposes said first metal pad;
a second metal pad connected to said first metal pad through said opening in said passivation layer, wherein the position of said second metal pad from a top perspective view is different from that of said first metal pad, and wherein said second metal pad comprises a gold layer having a thickness greater than 1 micrometer;
an adhesion/barrier layer directly on and in contact with said gold layer of said second metal pad;
a copper layer over said adhesion/barrier layer;
a nickel-containing layer over said copper layer; and
a tin-containing bump over said nickel-containing layer.
2. The chip of claim 1 , wherein said tin-containing bump has a height greater than 3 micrometers.
3. The chip of claim 1 , wherein said tin-containing bump has a height greater than 15 micrometers.
4. The chip of claim 1 , wherein said second metal pad further comprises a titanium-containing layer under said gold layer.
5. The chip of claim 1 , wherein said tin-containing bump layer comprises silver.
6. The chip of claim 1 , wherein said tin-containing bump layer comprises lead.
7. The chip of claim 1 , wherein said first metal pad comprises electroplated copper.
8. The chip of claim 1 , wherein said first metal pad comprises aluminum.
9. The chip of claim 1 , wherein said gold layer is electroplated.
10. The chip of claim 1 , wherein said passivation layer comprises a silicon-nitride layer.
11. The chip of claim 1 further comprising a polymer layer between said second metal pad and said passivation layer.
12. The chip of claim 11 , wherein said polymer layer comprises polyimide.
13. The chip of claim 1 further comprising a polymer layer over said passivation layer, wherein an opening in said polymer layer exposes said second metal pad.
14. The chip of claim 13 , wherein said polymer layer 5 comprises polyimide.
15. A chip comprising:
a semiconductor substrate;
a MOS device in or on said semiconductor substrate;
a first metal pad over said semiconductor substrate;
a passivation layer over said semiconductor substrate, wherein an opening in said passivation layer exposes said first metal pad;
a second metal pad connected to said first metal pad through said opening in said passivation layer, wherein the position of said second metal pad from a top perspective view is different from that of said first metal pad, and wherein said second metal pad comprises a titanium-containing layer and a gold layer over said titanium-containing layer;
an adhesion/barrier layer directly on and in contact with said gold layer of said second metal pad;
a copper layer over said adhesion/barrier layer;
a nickel-containing layer over said copper layer; and
a tin-containing bump over said nickel-containing layer.
16. The chip of claim 15 , wherein said tin-containing bump has a height greater than 3 micrometers.
17. The chip of claim 15 , wherein said tin-containing bump has a height greater than 15 micrometers.
18. The chip of claim 15 , wherein said gold layer has a thickness greater than 1 micrometer.
19. The chip of claim 15 , wherein said tin-containing bump comprises silver.
20. The chip of claim 15 , wherein said tin-containing bump comprises lead.
21. The chip of claim 15 , wherein said first metal pad comprises electroplated copper.
22. The chip of claim 15 , wherein said first metal pad comprises aluminum.
23. The chip of claim 15 , wherein said gold layer is electroplated.
24. The chip of claim 15 , wherein said passivation layer comprises a silicon-nitride layer.
25. The chip of claim 15 further comprising a polymer layer between said second metal pad and said passivation layer.
26. The chip of claim 25 , wherein said polymer layer comprises polyimide.
27. The chip of claim 15 further comprising a polymer layer over said passivation layer, wherein an opening in said polymer layer exposes said second metal pad.
28. The chip of claim 27 , wherein said polymer layer comprises polyimide.
29. A chip package comprising:
a first chip comprising a semiconductor substrate, a MOS device in or on said semiconductor substrate, a first metal pad over said semiconductor substrate, a passivation layer over said semiconductor substrate, wherein an opening in said passivation layer exposes said first metal pad, and a second metal pad connected to said first metal pad through said opening in said passivation layer, wherein said second metal pad comprises a copper layer and a nickel layer over said copper layer;
a second chip over said first chip; and
a tin-containing bump connecting said second metal pad to said second chip,
wherein said tin-containing bump is directly on and in contact with said nickel layer of said second metal pad, and wherein said tin-containing bump comprises silver.
30. The chip package of claim 29 further comprising an underfill between said first and second chips, wherein said underfill encloses said tin-containing bump.
31. The chip package of claim 29 , wherein said tin-containing bump further comprises copper.
32. The chip package of claim 29 , wherein said passivation layer comprises a silicon-nitride layer.
33. The chip package of claim 29 , wherein said first metal pad comprises electroplated copper.
34. The chip package of claim 29 , wherein said first metal pad comprises aluminum.
35. The chip package of claim 29 , wherein said second metal pad comprises a gold layer under said copper layer.
36. The chip package of claim 35 , wherein said gold layer has a thickness greater 1 micrometer.
37. The chip package of claim 35 , wherein said gold layer is electroplated.
38. The chip package of claim 35 , wherein said second metal pad further comprises a titanium-containing layer under said gold layer.
39. The chip package of claim 29 , wherein said passivation layer comprises a silicon-oxynitride layer.
40. The chip package of claim 29 , wherein said passivation layer has a thickness greater than 0.35 micrometers.
41. The chip package of claim 29 further comprising a polymer layer between said second metal pad and said passivation layer.
42. The chip package of claim 41 , wherein said polymer layer comprises polyimide.
43. The chip package of claim 29 further comprising a polymer layer over said passivation layer, wherein an opening in said polymer layer exposes said second metal pad.
44. The chip package of claim 43 , wherein said polymer layer comprises polyimide.