Integrated chip package structure using silicon substrate and method of manufacturing the same
View Patent ↗An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
1. A chip package comprising:
a substrate having a surface;
a die-surrounding layer directly on said surface of said substrate;
a die having a backside surface directly on said surface of said substrate, said die disposed between a first portion of said die-surrounding layer and a second portion of said die-surrounding layer, wherein said die has an active surface substantially coplanar with a first surface of said die-surrounding layer, wherein said die comprises a conductive pad within said active surface of said die;
a first dielectric layer on said active surface of said die and said first surface of said die-surrounding layer;
a first patterned conductive layer on said first dielectric layer, on said active surface of said die and on said first surface of said die-surrounding layer, wherein said first patterned conductive layer is coupled to said conductive pad of said die through an opening in said first dielectric layer;
a second dielectric layer on said first patterned conductive layer and on said first dielectric layer;
a second patterned conductive layer on said second dielectric layer, wherein said second patterned conductive layer is coupled to said first patterned conductive layer through an opening in a said second dielectric layer, in which said second patterned conductive layer comprises a portion configured for external coupling of said die; and
a comb-shaped capacitor disposed between said first patterned conductive layer and said second patterned conductive layer.
2. The chip package in claim 1 , wherein said comb-shaped capacitor is aligned with said first portion of said die-surrounding layer.
3. The chip package in claim 1 , wherein said first dielectric layer comprises polyimide.
4. The chip package in claim 1 , wherein said first dielectric layer comprises benzocyclobutene (BCB).
5. The chip package in claim 1 , wherein said first patterned conductive layer comprises electroplated copper.
6. The chip package in claim 1 , wherein said second dielectric layer comprises polyimide.
7. The chip package in claim 1 , wherein said second dielectric layer comprises benzocyclobutene (BCB).
8. The chip package in claim 1 further comprising multiple solder bumps, configured for external connection, aligned with said first surface of said die-surrounding layer.
9. The chip package in claim 1 further comprising multiple gold bumps, configured for external coupling being aligned with said first surface of said die-surrounding layer.
10. The chip package in claim 1 , wherein said substrate comprises a silicon substrate.
11. The chip package in claim 1 , wherein said die-surrounding layer comprises epoxy.
12. A chip package comprising:
a substrate having a surface;
a die-surrounding layer directly on said surface of said substrate;
a die having a backside surface directly on said surface of said substrate, said die disposed between a first portion of said die-surrounding layer and a second portion of said die-surrounding layer, wherein said die has an active surface substantially coplanar with a first surface of said die-surrounding layer, wherein said die comprises a first conductive pad and a second conductive pad within said active surface;
a first dielectric layer on said active surface of said die and on said first surface of said die-surrounding layer; and
a patterned conductive layer on said first dielectric layer, on said active surface of said die and on said first surface of said die-surrounding layer, wherein said patterned conductive layer is coupled to said first conductive pad of said die through a first opening in said first dielectric layer, and wherein said patterned conductive layer is coupled to said second conductive pad of said die through a second opening in said first dielectric layer, wherein said first conductive pad is coupled to said second conductive pad through said patterned conductive layer, wherein said patterned conductive layer comprises a portion of a passive device formed in said patterned conductive layer in a single horizontal plane and a portion configured for external coupling of said die.
13. The chip package in claim 12 , wherein said die-surrounding layer comprises epoxy.
14. The chip package in claim 12 further comprising multiple solder bumps, configured for external connection, vertically over said first surface of said die-surrounding layer.
15. The chip package in claim 12 , wherein said first dielectric layer comprises polyimide.
16. The chip package in claim 12 , wherein said first dielectric layer comprises benzocyclobutene (BCB).
17. The chip package in claim 12 further comprising a second dielectric layer on said patterned conductive layer and on said first dielectric layer.
18. The chip package in claim 17 , wherein said second dielectric layer comprises polyimide.
19. The chip package in claim 17 , wherein said second dielectric layer comprises benzocyclobutene (BCB).
20. The chip package in claim 12 , wherein said patterned conductive layer comprises a ground bus coupling said first conductive pad to said second conductive pad.
21. The chip package in claim 12 , wherein said patterned conductive layer comprises a power bus coupling said first conductive pad to said second conductive pad.
22. The chip package in claim 12 , wherein said patterned conductive layer comprises a signal trace coupling said first conductive pad to said second conductive pad.
23. The chip package in claim 12 , wherein said passive device comprises a micro electro mechanical sensor.
24. The chip package in claim 12 , wherein said passive device comprises an inductor.
25. The chip package in claim 12 , wherein said passive device comprises a capacitor.
26. The chip package in claim 12 , wherein said passive device comprises a resistor.
27. The chip package in claim 1 , wherein said substrate comprises a silicon substrate.
28. The chip package in claim 12 , wherein said portion of said passive device is aligned with said first portion of said die-surrounding layer.
29. A chip package comprising:
a substrate having a surface;
a die-surrounding layer directly on said surface of said substrate;
a die having a backside surface directly on said surface of said substrate, said die disposed between a first portion of said die-surrounding layer and a second portion of said die-surrounding layer, wherein said die has an active surface substantially coplanar with a first surface of said die-surrounding layer, wherein said die comprises a first conductive pad and a second conductive pad within said active surface;
a first dielectric layer on said active surface of said die and on said first surface of said die-surrounding layer; and
a patterned conductive layer on said first dielectric layer, on said active surface of said die and on said first surface of said die-surrounding layer, wherein said patterned conductive layer comprises a ground piece coupled to said first conductive pad of said die through a first opening in said first dielectric layer, and coupled to said second conductive pad of said die through a second opening in said first dielectric layer, wherein said first conductive pad is coupled to said second conductive pad through said ground piece, wherein said patterned conductive layer comprises a portion of a passive device formed in said patterned conductive layer and a portion configured for external coupling of said die.
30. The chip package in claim 29 , wherein said passive device comprises an inductor.
31. The chip package in claim 29 , wherein said passive device comprises a resistor.
32. The chip package in claim 29 , wherein said die-surrounding layer comprises epoxy.
33. The chip package in claim 29 , wherein said passive device comprises a capacitor.
34. The chip package in claim 29 , wherein said first dielectric layer comprises polyimide.
35. The chip package in claim 29 further comprising a second dielectric layer on said patterned conductive layer and said first dielectric layer.
36. The chip package in claim 29 , wherein said first dielectric layer comprises benzocyclobutene (BCB).
37. The chip package in claim 29 further comprising multiple solder bumps, configured for external coupling aligned with said first surface of said die-surrounding layer.
38. The chip package in claim 29 further comprising a substrate supporting said die and said first and second portions of said die-surrounding layer.
39. The chip package in claim 29 , wherein said substrate comprises a silicon substrate.
40. The chip package in claim 29 , wherein said passive device comprises a micro electro mechanical sensor.
41. The chip package in claim 29 , wherein said patterned conductive layer comprises electroplated copper.
42. The chip package in claim 12 , wherein said patterned conductive layer comprises electroplated copper.