Chip structure and process for forming the same
View Patent ↗A chip or wafer comprises a semiconductor substrate, first and second transistors on the semiconductor substrate, first and second metal layers over the semiconductor substrate, an insulating layer on the first and second metal layers, a third and fourth metal layers on the insulating layer, a passivation layer over the third and fourth metal layers, and a fifth metal layer over the passivation layer. A signal is suited to be transmitted from the first transistor to the second transistor sequentially through the first, third, fifth, fourth and second metal layers.
1. A chip, comprising:
a silicon substrate;
a first transistor in or on said silicon substrate;
a second transistor in or on said silicon substrate;
a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure comprises a first portion and a second portion over said first portion, wherein said first portion is connected to said second portion;
a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure comprises a third portion and a fourth portion over said third portion, wherein said third portion is connected to said fourth portion, wherein said first interconnecting structure is separate from said second interconnecting structure, wherein said first and third portions are provided by a first metal layer, and said second and fourth portions are provided by a second metal layer over said first metal layer;
an insulating layer between said first and second metal layers;
a passivation layer over said first and second interconnecting structures and over said insulating layer, wherein said passivation layer comprises a topmost nitride layer of said chip, wherein a first opening in said passivation layer exposes a first pad of said first interconnecting structure, and a second opening in said passivation layer exposes a second pad of said second interconnecting structure, wherein said first opening has a width between 0.5 and 20 micrometers; and
a third interconnecting structure over said passivation layer and over said first and second pads, wherein said first transistor is connected to said second transistor through, in sequence, said first interconnecting structure, said first opening, said third interconnecting structure, said second opening and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a thickness greater than 1 micrometer and greater than those of said first and second metal layers, and having a width greater than 1 micrometer.
2. The chip of claim 1 , wherein said third interconnecting structure comprises gold.
3. The chip of claim 1 , wherein said third interconnecting structure comprises copper.
4. The chip of claim 1 , wherein said third interconnecting structure comprises aluminum.
5. The chip of claim 1 further comprising a polymer layer over said third interconnecting structure.
6. The chip of claim 1 further comprising a polymer layer over said passivation layer, wherein said third interconnecting structure comprises a third metal layer and a fourth metal layer over said third metal layer, wherein said polymer layer is between said third and fourth metal layers.
7. The chip of claim 1 further comprising a polymer layer between said passivation layer and said third interconnecting structure.
8. A wafer, comprising:
a silicon substrate;
a first transistor in or on said silicon substrate;
a second transistor in or on said silicon substrate;
a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure comprises a first portion and a second portion over said first portion, wherein said first portion is connected to said second portion;
a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure comprises a third portion and a fourth portion over said third portion, wherein said third portion is connected to said fourth portion, wherein said first interconnecting structure is separate from said second interconnecting structure, wherein said first and third portions are provided by a first metal layer, and said second and fourth portions are provided by a second metal layer over said first metal layer;
an insulating layer between said first and second metal layers;
a passivation layer over said first and second interconnecting structures and over said insulating layer, wherein said passivation layer comprises a topmost nitride layer of said wafer, wherein a first opening in said passivation layer exposes a first pad of said first interconnecting structure, and a second opening in said passivation layer exposes a second pad of said second interconnecting structure, wherein said first opening has a width between 0.5 and 20 micrometers;
a first polymer layer over said passivation layer, wherein a third opening in said first polymer layer exposes said first pad, and a fourth opening in said first polymer layer exposes said second pad, wherein said first polymer layer has a thickness greater than those of said insulating layer and said passivation layer; and
a third interconnecting structure over said first polymer layer and over said first and second pads, wherein said first transistor is connected to said second transistor through, in sequence, said first interconnecting structure, said third opening, said third interconnecting structure, said fourth opening and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a thickness greater than 1 micrometer and greater than those of said first and second metal layers, and having a width greater than 1 micrometer.
9. The wafer of claim 8 , wherein said third interconnecting structure comprises gold.
10. The wafer of claim 8 , wherein said third interconnecting structure comprises copper.
11. The wafer of claim 8 , wherein said third interconnecting structure comprises aluminum.
12. The wafer of claim 8 further comprising forming a second polymer layer over said third interconnecting structure.
13. The wafer of claim 8 further comprising a second polymer layer over said passivation layer, wherein said third interconnecting structure comprises a third metal layer and a fourth metal layer over said third metal layer, wherein said polymer layer is between said third and fourth metal layers.
14. The wafer of claim 8 , wherein said third opening further exposes said passivation layer.
15. The wafer of claim 8 , wherein said third interconnecting structure comprises nickel.
16. The wafer of claim 8 , wherein said third interconnecting structure comprises an electroplated metal.
17. The wafer of claim 8 , wherein said third interconnecting structure comprises titanium.
18. The chip of claim 1 , wherein said third interconnecting structure comprises nickel.
19. The chip of claim 1 , wherein said third interconnecting structure comprises an electroplated metal.
20. The chip of claim 1 , wherein said third interconnecting structure comprises titanium.