Mechanism for resource allocation in a digital signal processor based on instruction type information and functional priority and method of operation thereof
View Patent ↗A mechanism for resource allocation in a processor, a method of allocating resources in a processor and a digital signal processor incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) categorization logic, associated with an earlier pipeline stage, that generates instruction type information for instructions to be executed in the processor and (2) priority logic, associated with a later pipeline stage, that allocates functional units of the processor to execution of the instructions based on the instruction type information.
1. A mechanism for resource allocation in a processor, comprising:
categorization logic, associated with an earlier pipeline stage, that generates instruction type information for instructions to be executed in said processor;
queuing logic, in which said instructions and said instruction type information are stored in an order based on a priority of said instructions derived from a priority of functional units in said processor; and
priority logic, associated with a later pipeline stage, that allocates functional units of said processor to execution of said instructions in said order based on said instruction type information.
2. The mechanism as recited in claim 1 wherein said categorization logic causes said instruction type information to be stored and tagged in a queue containing said instructions.
3. The mechanism as recited in claim 1 wherein said earlier pipeline stage is a fetch/decode stage of said processor.
4. The mechanism as recited in claim 1 wherein said instructions are ungrouped when said categorization logic generates said instruction type information.
5. The mechanism as recited in claim 1 wherein said instruction type information defines at least four categories of instruction.
6. The mechanism as recited in claim 1 wherein said priority logic employs separate allocation schemes depending upon categories defined by said instruction type information.
7. The mechanism as recited in claim 1 wherein said processor is a digital signal processor.
8. A method of allocating resources in a processor, comprising:
generating instruction type information for instructions to be executed in said processor in an earlier clock cycle thereof;
storing said instructions and said instruction type information in a queue in an order based on a priority of said instructions derived from a priority of functional units in said processor; and
allocating functional units of said processor to execution of said instructions in said order based on said instruction type information in a later clock cycle of said processor.
9. The method as recited in claim 8 further comprising storing said instruction type information is tagged in a queue containing said instructions.
10. The method as recited in claim 8 wherein said generating is carried out in a fetch/decode stage of said processor.
11. The method as recited in claim 8 wherein said instructions are ungrouped when said generating is carried out.
12. The method as recited in claim 8 wherein said instruction type information defines at least four categories of instruction.
13. The method as recited in claim 8 wherein said allocating comprises employing separate allocation schemes depending upon categories defined by said instruction type information.
14. The method as recited in claim 8 wherein said processor is a digital signal processor.
15. A digital signal processor (DSP), comprising:
a pipeline having stages;
functional units coupled to said pipeline;
an instruction issue unit, coupled to said functional units, that wide-issues instructions for execution in said functional units;
categorization logic, associated with an earlier stage of said pipeline, that generates instruction type information for said instructions;
queuing, in which said instructions and said instruction type information are stored in an order based on a priority of said instructions derived from a priority of functional units in said processor; and
priority logic, associated with a later stage of said pipeline, that allocates said functional units to said execution of said instructions in said order based on said instruction type information.
16. The DSP as recited in claim 15 wherein said categorization logic causes said instruction type information to be stored and tagged in a categorization queue located in said instruction issue unit and containing said instructions.
17. The DSP as recited in claim 15 wherein said earlier stage is a fetch/decode stage.
18. The DSP as recited in claim 15 wherein said instructions are ungrouped when said categorization logic generates said instruction type information.
19. The DSP as recited in claim 15 wherein said instruction type information defines at least four categories of instruction.
20. The DSP as recited in claim 15 wherein said priority logic employs separate allocation schemes depending upon categories defined by said instruction type information.