Patent Assignment
Reel/Frame 049971/0525
Release of Security Interest
Recorded: 2019-08-06
Pages: 3
Assignor
LSI LOGIC CORPORATION
Executed: 2014-04-29
Assignee
VERISILICON HOLDINGS CO., LTD.
4699 OLD IRONSIDE DRIVE, SUITE 270, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(33)
Alternate Booth Partial Product Generation for a Hardware Multiplier
Patent:
6,622,154 →
Application:
09/467,939 →
Bridge for Coupling Digital Signal Processor to on-Chip Bus as Master
Patent:
6,687,773 →
Application:
09/847,849 →
Bridge for Coupling Digital Signal Processor to on-Chip Bus as Slave
Patent:
6,789,153 →
Application:
09/847,850 →
Increasing Dsp Efficiency by Independent Issuance of Store Address and Data
Patent:
6,963,961 →
Application:
09/901,455 →
Instruction Fusion for Digital Signal Processor
Patent:
6,889,318 →
Application:
09/924,178 →
System and Method for Extracting Instruction Boundaries in a Fetched Cacheline, Given an Arbitrary Offset Within the Cacheline
Patent:
6,961,844 →
Application:
09/972,404 →
Integrated Circuit Containing Multiple Digital Signal Processors
Patent:
6,959,376 →
Application:
09/975,677 →
Conditional Link Pointer Register Sets Marking the Beginning and End of a Conditional Instruction Block Where Each Set Corresponds to a Single Stage of a Pipeline That Moves Link Pointers Through Each Corresponding Register of Said Register Sets as Instructions Move Through the Pipeline
Patent:
7,251,721 →
Application:
09/993,114 →
Efficient Memory Management Mechanism for Digital Signal Processor and Method of Operation Thereof
Patent:
6,715,038 →
Application:
09/993,431 →
Mechanism and Method for Reducing Pipeline Stalls Between Nested Calls and Digital Signal Processor Incorporating the Same
Patent:
7,013,382 →
Application:
10/002,817 →
Pipelined Multiply-Accumulate Unit and Out-of-Order Completion Logic for a Superscalar Digital Signal Processor and Method of Operation Thereof
Patent:
7,231,510 →
Application:
10/007,498 →
Mechanism for Supporting Self-Modifying Code in a Harvard Architecture Digital Signal Processor and Method of Operation Thereof
Patent:
6,871,247 →
Application:
10/007,555 →
Changing Instruction Order by Reassigning Only Tags in Order Tag Field in Instruction Queue
Patent:
6,813,704 →
Application:
10/028,898 →
Pipeline Stall Reduction in Wide Issue Processor by Providing Mispredict Pc Queue and Staging Registers to Track Branch Instructions in Pipeline
Patent:
6,976,156 →
Application:
10/047,515 →
Mechanism for Resource Allocation in a Digital Signal Processor Based on Instruction Type Information and Functional Priority and Method of Operation Thereof
Patent:
7,107,433 →
Application:
10/066,147 →
Efficient Instruction Prefetch Mechanism Employing Selective Validity of Cached Instructions for Digital Signal Processor and Method of Operation Thereof
Patent:
7,085,916 →
Application:
10/066,150 →
System and Method for Executing Software Program Instructions Using a Condition Specified Within a Conditional Execution Instruction
Patent:
7,434,036 →
Application:
10/231,948 →
Marking Queue for Simultaneous Execution of Instructions in Code Block Specified by Conditional Execution Instruction
System and Method for Cooperative Execution of Multiple Branching Instructions in a Processor
System, Circuit, and Method for Adjusting the Prefetch Instruction Rate of a Prefetch Unit
Patent:
7,103,757 →
Application:
10/277,339 →
Circuit and Method for Improving Instruction Fetch Time from a Cache Memory Device
Patent:
6,968,430 →
Application:
10/277,341 →
In-Circuit Emulation Debugger and Method of Operation Thereof
Patent:
7,360,117 →
Application:
10/279,344 →
Distributed Result System for High-Performance Wide-Issue Superscalar Processor
System and Method for Evaluating and Efficiently Executing Conditional Instructions
Patent:
7,275,149 →
Application:
10/396,265 →
System and Method for Reference-Modeling a Processor
Patent:
6,973,630 →
Application:
10/408,387 →
System and Method for Electrical Power Management in a Data Processing System Using Registers to Reflect Current Operating Conditions
System and Method for Cooperative Operation of a Processor and Coprocessor
Data Processing Systems Including High Performance Buses and Interfaces, and Associated Communication Methods
Processor and Method for Convolutional Decoding
Asynchronous Data Structure for Storing Data Generated by a Dsp System
Patent:
6,956,788 →
Application:
10/701,775 →
Hardware Looping Mechanism and Method for Efficient Execution of Discontinuity Instructions
Patent:
7,272,704 →
Application:
10/844,941 →
Digital Signal Processor Having Inverse Discrete Cosine Transform Engine for Video Decoding and Partitioned Distributed Arithmetic Multiply/Accumulate Unit Therefor
Patent:
7,574,468 →
Application:
11/083,575 →
Simultaneously Assigning Corresponding Entry in Multiple Queues of Multi-Stage Entries for Storing Condition Attributes for Validating Simultaneously Executed Conditional Execution Instruction Groups
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name
Aug 6, 2019
From: VERISILICON HOLDINGS (CAYMAN ISLANDS) CO. LTD.
To: VERISILICON HOLDINGS CO., LTD.
Reel/Frame 050122/0833 →
Change of Address
Mar 19, 2020
From: VERISILICON HOLDINGSCO., LTD.
To: VERISILICON HOLDINGSCO., LTD.
Reel/Frame 052189/0438 →
Change of Address
Jan 8, 2021
From: VERISILICON HOLDINGS CO., LTD.
To: VERISILICON HOLDINGS CO., LTD.
Reel/Frame 054927/0651 →