Conditional link pointer register sets marking the beginning and end of a conditional instruction block where each set corresponds to a single stage of a pipeline that moves link pointers through each corresponding register of said register sets as instructions move through the pipeline
View Patent ↗For use in a wide-issue processor, a mechanism for, and method of, conditionally executing instructions and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a conditional execution block state machine that tags and generates link pointers for instructions located in a conditional execution block and (2) conditional link pointer registers, associated with stages in a pipeline of the processor, that contain and cause the link pointers to move therethrough as the instructions located in the conditional execution block move through the stages.
1. For use in a wide-issue processor, a mechanism for identifying and tracking conditional instructions, comprising:
a conditional execution block state machine that tags and generates contemporaneous link pointers for instructions located in a conditional execution block, wherein said link pointers mark at least the beginning and end of a conditional execution block of instructions; and
conditional link pointer register sets, wherein each of said register sets corresponds to a single stage of a pipeline of said processor, that contain and cause said link pointers to move through each corresponding register of said register sets as said instructions associated with said link pointers and located in said conditional execution block move through each of said corresponding stages, said corresponding stages including a fetch/decode stage and a group stage.
2. The mechanism as recited in claim 1 further comprising a conditional execution marking queue, associated with said conditional execution block state machine, that contains ones of said link pointers prior to storage in said sets.
3. The mechanism as recited in claim 2 wherein said conditional execution marking queue is a five-bit, six-entry queue and comprises a reordering multiplexer.
4. The mechanism as recited in claim 1 further comprising a conditional execution attribute register, associated with a group stage of said pipeline, that contains an attribute associated with one of said conditional instructions.
5. The mechanism as recited in claim 4 further comprising a conditional execution attribute queue that contains attributes read from said conditional execution attribute register.
6. The mechanism as recited in claim 5 wherein said conditional execution attribute queue is of variable depth and comprises a selecting multiplexer.
7. The mechanism as recited in claim 1 , wherein:
said fetch/decode stage is configured to:
fetch and decode instructions;
identify conditional execution instructions; and
generate said link pointers; and
said group stage is configured to:
check grouping and dependency rules;
group valid instructions;
execute return instructions; and
group conditional execution instructions and blocks.
8. A wide-issue digital signal processor (DSP), comprising:
a pipeline having stages capable of executing instructions conditionally;
a wide-issue instruction issue unit;
a conditional execution block state machine, associated with said instruction issue unit, that tags and generates contemporaneous link pointers for instructions located in a conditional execution block, wherein said link pointers mark at least the beginning and end of a conditional execution block of instructions; and
conditional link pointer register sets, wherein each of said register sets corresponds to a single stage of a pipeline of said processor, that contain and cause said link pointers to move through each corresponding register of said register sets as said instructions associated with said link pointers and located in said conditional execution block move through each of said corresponding stages, said corresponding stages including a fetch/decode stage and a group stage.
9. The DSP as recited in claim 8 further comprising a conditional execution marking queue, associated with said conditional execution block state machine, that contains ones of said link pointers prior to storage in said sets.
10. The DSP as recited in claim 9 wherein said conditional execution marking queue is a five-bit, six-entry queue and comprises a reordering multiplexer.
11. The DSP as recited in claim 8 further comprising a conditional execution attribute register, associated with a group stage of said pipeline, that contains an attribute associated with one of said conditional instructions.
12. The DSP as recited in claim 11 further comprising a conditional execution attribute queue that contains attributes read from said conditional execution attribute register.
13. The DSP as recited in claim 12 wherein said conditional execution attribute queue is of variable depth and comprises a selecting multiplexer.
14. The DSP as recited in claim 8 , wherein:
said fetch/decode stage is configured to:
fetch and decode instructions;
identify conditional execution instructions; and
generate said link pointers; and
said group stage is configured to:
check grouping and dependency rules;
group valid instructions;
execute return instructions; and
group conditional execution instructions and blocks.