Patent Assignment
Reel/Frame 017906/0143
Security Interest
Recorded: 2006-07-07
Received: 2006-07-07
Pages: 13
Assignor
VERISILICON HOLDINGS (CAYMAN ISLANDS) CO., LTD.
Executed: 2006-07-07
Assignee
LSI LOGIC CORPORATION
1621 BARBER LANE, MS AD-106, MILPITAS, CA, 95035, UNITED STATES
Covered Properties
(37)
Simultaneously Assigning Corresponding Entry in Multiple Queues of Multi-Stage Entries for Storing Condition Attributes for Validating Simultaneously Executed Conditional Execution Instruction Groups
Application:
11/273,679 →
Processor implementing conditional execution and including a serial queue
Application:
11/246,595 →
Branch predictor for a processor and method of predicting a conditional branch
Application:
11/222,533 →
Digital Signal Processor Having Inverse Discrete Cosine Transform Engine for Video Decoding and Partitioned Distributed Arithmetic Multiply/Accumulate Unit Therefor
Application:
11/083,575 →
Hardware Looping Mechanism and Method for Efficient Execution of Discontinuity Instructions
Application:
10/844,941 →
Asynchronous Data Structure for Storing Data Generated by a Dsp System
Application:
10/701,775 →
Processor and Method for Convolutional Decoding
Application:
10/613,128 →
Data Processing Systems Including High Performance Buses and Interfaces, and Associated Communication Methods
Application:
10/603,303 →
System and Method for Cooperative Operation of a Processor and Coprocessor
Application:
10/437,485 →
System and Method for Electrical Power Management in a Data Processing System Using Registers to Reflect Current Operating Conditions
Application:
10/420,581 →
System and Method for Reference-Modeling a Processor
Application:
10/408,387 →
System and Method for Evaluating and Efficiently Executing Conditional Instructions
Application:
10/396,265 →
Distributed Result System for High-Performance Wide-Issue Superscalar Processor
Application:
10/310,234 →
Processor having a unified register file with multipurpose registers for storing both address and data register values,a processor having an instruction decoder and an associated register mapping method
Application:
10/299,532 →
In-Circuit Emulation Debugger and Method of Operation Thereof
Application:
10/279,344 →
System, Circuit, and Method for Adjusting the Prefetch Instruction Rate of a Prefetch Unit
Application:
10/277,339 →
Circuit and Method for Improving Instruction Fetch Time from a Cache Memory Device
Application:
10/277,341 →
System and method for efficient execution of load/store with update instructions by conditional update of a pointer
Application:
10/262,414 →
System and Method for Cooperative Execution of Multiple Branching Instructions in a Processor
Application:
10/256,864 →
Marking Queue for Simultaneous Execution of Instructions in Code Block Specified by Conditional Execution Instruction
Application:
10/256,410 →
System and Method for Executing Software Program Instructions Using a Condition Specified Within a Conditional Execution Instruction
Application:
10/231,948 →
Changing Instruction Order by Reassigning Only Tags in Order Tag Field in Instruction Queue
Application:
10/028,898 →
Pipelined Multiply-Accumulate Unit and Out-of-Order Completion Logic for a Superscalar Digital Signal Processor and Method of Operation Thereof
Application:
10/007,498 →
Mechanism for Supporting Self-Modifying Code in a Harvard Architecture Digital Signal Processor and Method of Operation Thereof
Application:
10/007,555 →
Efficient Memory Management Mechanism for Digital Signal Processor and Method of Operation Thereof
Application:
09/993,431 →
Conditional Link Pointer Register Sets Marking the Beginning and End of a Conditional Instruction Block Where Each Set Corresponds to a Single Stage of a Pipeline That Moves Link Pointers Through Each Corresponding Register of Said Register Sets as Instructions Move Through the Pipeline
Application:
09/993,114 →
Mechanism and Method for Reducing Pipeline Stalls Between Nested Calls and Digital Signal Processor Incorporating the Same
Application:
10/002,817 →
Efficient Instruction Prefetch Mechanism Employing Selective Validity of Cached Instructions for Digital Signal Processor and Method of Operation Thereof
Application:
10/066,150 →
Pipeline Stall Reduction in Wide Issue Processor by Providing Mispredict Pc Queue and Staging Registers to Track Branch Instructions in Pipeline
Application:
10/047,515 →
Mechanism for Resource Allocation in a Digital Signal Processor Based on Instruction Type Information and Functional Priority and Method of Operation Thereof
Application:
10/066,147 →
Integrated Circuit Containing Multiple Digital Signal Processors
Application:
09/975,677 →
System and Method for Extracting Instruction Boundaries in a Fetched Cacheline, Given an Arbitrary Offset Within the Cacheline
Application:
09/972,404 →
Instruction Fusion for Digital Signal Processor
Application:
09/924,178 →
Increasing Dsp Efficiency by Independent Issuance of Store Address and Data
Application:
09/901,455 →
Bridge for Coupling Digital Signal Processor to on-Chip Bus as Slave
Application:
09/847,850 →
Bridge for Coupling Digital Signal Processor to on-Chip Bus as Master
Application:
09/847,849 →
Methods and Apparatus for Generating, Including and Using Information Relating to Archived Audio/Video Data
Application:
09/839,354 →