Marking queue for simultaneous execution of instructions in code block specified by conditional execution instruction
View Patent ↗A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple state machines simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes multiple attribute queues simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes write enable logic and an execution unit. The write enable logic produces write enable signals dependent upon received attributes, and the execution unit saves results of instructions of conditional execution instruction groups dependent upon the write enable signals.
1. A conditional execution marking queue associated with a grouping pipeline stage of a processor, comprising:
a conditional execution instruction monitor, associated with a conditional execution instruction group having a conditional execution instruction and a corresponding code block of instructions specified by the conditional execution instruction, and configured to generate marking data for each of a plurality of instructions grouped together in the grouping pipeline stage for simultaneous execution, wherein the plurality of instructions include at least one instruction of the associated conditional execution instruction group and the marking data indicates whether each of the plurality of instructions is an instruction of the associated conditional execution instruction group, and
a marking queue configured to store the marking data.
2. The conditional execution marking queue as recited in claim 1 , wherein the conditional execution instruction group resides in a section of code retrieved by the processor from a memory system.
3. The conditional execution marking queue as recited in claim 2 further comprising a plurality of conditional execution instruction monitors, wherein the memory system includes a plurality of conditional execution instruction groups and each of the plurality of conditional execution instruction monitors is simultaneously associated with a distinct one of the conditional execution instruction groups.
4. The conditional execution marking queue as recited in claim 1 , wherein the conditional execution instruction specifies a condition, and wherein a result of each of the instructions of the code block is saved dependent upon the existence of the specified condition in the processor during execution of the conditional execution instruction.
5. The conditional execution marking queue as recited in claim 3 , wherein at least one of the plurality of conditional execution instruction monitors is a finite state machine.
6. The conditional execution marking queue as recited in claim 1 , wherein the marking data generated for each of the instructions indicates that the instruction is either: not an instruction of the assigned conditional execution instruction group, a first instruction of the assigned conditional execution instruction group, a last instruction of the assigned conditional execution instruction group, or an instruction of the assigned conditional execution instruction group.
7. The conditional execution marking queue as recited in claim 3 , wherein when a number of the conditional execution instruction monitors are less than a number of conditional execution instruction groups, the conditional execution instruction monitors are simultaneously assignable to a different one of the conditional execution instruction groups.
8. The conditional execution marking queue as recited in claim 1 wherein the conditional execution marking queue is employed in the processor.