Asynchronous data structure for storing data generated by a DSP system
View Patent ↗In some embodiments, a system includes a memory device in a first clock domain region and a memory device and a digital signal processing (DSP) sub-system in a second clock domain region. In addition, a plurality of asynchronous first-in first-out (FIFO) data structures, each comprising a read interface, a write interface, and one or more data slots, store data generated from the DSP sub-system. The read interface operates in the first clock domain, and the write interface operates in the second clock domain.
1. A system, comprising:
a first clock domain region including a first memory device;
a second clock domain region including a second memory device and a digital signal processing (DSP) sub-system;
a plurality of asynchronous first-in first-out (FIFO) data structures that store data generated from the DSP sub-system, each FIFO including a read interface, a write interface, and one or more data slots; and
wherein the each read interface operates in the first clock domain and each write interface operates in the second clock domain.
2. The system of claim 1 , wherein each of the plurality of FIFO data structures generate a full signal indicating whether the FIFO data structure has data occupying all of the one or more data slots.
3. The system of claim 1 , wherein each of the plurality of FIFO data structures generate an empty signal indicating whether the FIFO data structure has data slots in which no data is stored.
4. The system of claim 1 , further comprising a processor operating in the second clock domain that interacts with the FIFO data structures by submitting requests to store data.
5. The system of claim 1 , wherein each of the plurality of FIFO data structures operate independently from each other.
6. The system of claim 1 , further comprising buffers that temporarily hold data generated from the DSP sub-system, wherein at least one of the buffers is coupled to each FIFO data structure.
7. The system of claim 1 , wherein the second memory device stores data that that is processed by the DSP sub-system, wherein the data comprises a set of data values that are stored in the first memory device.
8. The system of claim 1 , wherein the data stored by the plurality of FIFO data structures is encoded with a first protocol that is converted to a second protocol supported by the first memory device.
9. The system of claim 1 , wherein the date stored by the plurality of FIFO data structures is utilized by a cache coherency protocol employed in the DSP sub-system.
10. A method for performing asynchronous data transfers, comprising:
generating data from a digital signal processing (DSP) system;
storing the data into a plurality of asynchronous first-in first-out (FIFO) data structures with a write interface;
retrieving the data from the FIFO data structures through a read interface; and
wherein the write and the read interface operate in different clock domains.
11. The method of claim 10 , wherein the FIFO data structures comprise one or more data slots that store data in a serial fashion.
12. The method of claim 10 , further comprising generating a full signal from each FIFO data structure when the all of the one or more data slots associated with respective FIFO data structure are storing data.
13. The method of claim 10 , further comprising generating an empty signal from each FIFO data structure when the all of the one or more data slots associated with respective FIFO data structure are not storing data.
14. The method of claim 10 , further comprising converting the generated data to a protocol supported by the FIFO data structure.
15. A system, comprising:
a means for storing data in a first clock domain;
a means for storing data and a means for processing digital signals in a second clock domain;
a plurality of means for asynchronously storing data generated from the means for processing digital signals, each means for asynchronously storing data including a means for reading data, a means for writing data; and
wherein each means for reading data operates in the first clock domain and each means for writing data operates in the second clock domain.
16. The system of claim 15 , wherein each means for asynchronously storing data further comprises a means for generating a full signal that indicates whether the means for asynchronously storing data is currently full.
17. The system of claim 15 , wherein each means for asynchronously storing data further comprises a means for generating a empty signal that indicates whether the means for asynchronously storing data is currently empty.
18. The system of claim 15 , further comprising a mean for temporarily storing data, wherein means for temporarily storing data queues data generated by the means for processing digital signals before the data is stored in one of the plurality of means for asynchronously storing data.
19. The system of claim 15 , wherein each means for asynchronously storing data operates independently from each other.
20. The system of claim 15 , wherein the plurality of means for asynchronously storing data store data utilized by a means for coherently maintaining cache memory coupled to the means for processing digital signals.