IP Library Granted Patent US 6,954,130
Granted Patent B2
US 6,954,130 · App. 10/071,581 · Granted Oct 11, 2005

Integrated passive components and package with posts

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Quick Facts
Patent No.
US 6,954,130
App. No.
10/071,581
Granted
Oct 11, 2005
Kind
B2
Abstract

A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.

Claims (38)

1. A packaged inductor comprising:

a substrate;

a first insulating layer over the substrate;

posts over the insulating layer;

a conductive layer deposited on top of the posts and in a pattern on the substrate, the conductive layer on the tops of the posts for coupling the packaged inductor to another device.

2. The packaged inductor of claim 1 , further comprising:

a protective layer over the conductive layer, the posts, and the first insulating layer, the protective layer leaving exposed the conductive layer on the top of the posts.

3. The packaged inductor of claim 2 , wherein the protective layer is of polyimide which provides compliancy to the packaged inductor.

4. The packaged inductor of claim 3 , wherein the protective layer comprises a first layer of nickel and a second layer of flash gold.

5. The packaged inductor of claim 1 , wherein the first insulating layer is a polyimide layer which provides compliancy to the packaged inductor.

6. The packaged inductor of claim 1 , wherein the posts are made of one or more of the materials including: silicon, gallium arsenide, silicon germanium, silicon carbide, gallium phosphide, ceramic materials, sapphire, quartz, and other substrate materials.

7. The packaged inductor of claim 1 , wherein the conductive layer is gold.

8. A packaged inductor comprising:

a substrate including a plurality of posts having a top;

conductive layer a pattern on the substrate to form an inductor, the conductive layer extending to the top of the posts;

a first insulating layer over the conductive layer; and

the top of the posts used for coupling the packaged inductor to another device.

9. The packaged inductor of claim 8 , wherein the first insulating layer comprises a compliant material, the compliant material providing compliancy to the packaged inductor.

10. The packaged inductor of claim 9 , wherein the first insulating layer is a polyimide layer.

11. The packaged inductor of claim 8 , further comprising:

a protective layer over the conductive layer, the posts, and the first insulating layer.

12. The packaged inductor of claim 11 , wherein the protective layer is a polyimide to provide compliancy to the packaged inductor.

13. The packaged inductor of claim 11 , wherein the protective layer comprises a first layer of nickel, and a second layer of gold.

14. The packaged inductor of claim 8 , wherein the posts are made of one or more of the materials including: silicon, gallium arsenide, silicon germanium, silicon carbide, gallium phosphide, ceramic materials, sapphire, quartz, and other substrate materials.

15. The packaged inductor of claim 8 , wherein the conductive layer is gold.

16. The packaged inductor of claim 8 , wherein the pattern of the inductive layer is in a spiral pattern.

17. The packaged inductor of claim 16 , wherein the plurality of posts comprise a first post and a second post, the first post located at an inside end of the spiral pattern, and the second post located at an outside end of the spiral pattern.

18. The packaged inductor of claim 8 , further comprising:

a contact layer on the conductive layer on top of the posts, the contact layer designed to be directly in contact with a printer circuit board.

19. A packaged inductor comprising:

a substrate;

a passivation layer over the substrate;

an insulating layer over the passivation layer;

inside post and an outside post over the insulating layer;

a conductive layer over the top of the posts, the conductive layer deposited as a spiral pattern between the inside post and the outside post;

a fixing passivation layer to isolate the conductive layer, the fixing passivation layer leave a tops of the inside post and the outside post exposed; and

a contact layer on the conductive layer on the tops of the inside post and the outside post to protect the conductive layer, the contact layer designed to be placed in contact with a printed circuit board.

20. The packaged inductor of claim 19 , wherein the passivation layer is a compliant material, to provide compliancy to the packaged inductor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2012
From: MARCOUX, PHIL
To: CHIP SYSTEMS INNOVATIONS, LLC
Reel/Frame 028911/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2012
From: MARCOUX, PHIL P.; LECKRONE, DANIEL; TECHNOLOGY PROPERTIES LIMITED LLC; WAFER-LEVEL PACKAGING PORTFOLIO LLC; ALLIACENSE LIMITED LLC; INTELLASYS BEC LTD.
To: MARCOUX, PHIL P.
Reel/Frame 028417/0789 →