IP Library Assignment 028911/0296
Patent Assignment
Reel/Frame 028911/0296

Assignment of Assignor's Interest

Recorded: 2012-09-06 Pages: 6
Assignor
MARCOUX, PHIL
Executed: 2012-08-31
Assignee
CHIP SYSTEMS INNOVATIONS, LLC
335 CHATHAM WAY, MOUNTAIN VIEW, CALIFORNIA, 94040-4471
Covered Properties (22)
Fabricating a Semiconductor with an Insulative Coating
Patent: 5,403,729 →
Application: 07/889,832 →
Electrical Apparatus with a Metallic Layer Coupled to a Lower Region of a Substrate and Metallic Layer Coupled to a Lower Region of a Semiconductor Device
Patent: 5,280,194 →
Application: 07/940,763 →
Method for Making a Leadless Surface Mounted Device with Wrap-Around Flange Interface Contacts
Patent: 5,656,547 →
Application: 08/241,602 →
Fabricating a Semiconductor with an Insulative Coating
Patent: 5,521,420 →
Application: 08/270,784 →
Fabricating a Semiconductor with an Insulative Coating
Patent: 5,592,022 →
Application: 08/270,939 →
Method of Making a Semiconductor Device with a Metallic Layer Coupled to a Lower Region of a Substrate and Metallic Layer Coupled to a Lower Region of a Semiconductor Device
Patent: 5,455,187 →
Application: 08/331,783 →
Fabricating a Semiconductor with an Insulative Coating
Patent: 5,441,898 →
Application: 08/363,732 →
Fabricating a Semiconductor with an Insulative Coating
Patent: 5,444,009 →
Application: 08/363,733 →
Semiconductor Fabrication with Contact Processing for Wrap-Around Flange Interface
Patent: 5,557,149 →
Application: 08/409,994 →
Electrical Apparatus with a Metallic Layer Coupled to a Lower Region of a Substrate and a Metallic Layer Coupled to a Lower Region of a Semiconductor Device
Patent: 5,789,817 →
Application: 08/749,422 →
Wafer Fabrication of Die-Bottom Contacts for Electronic Devices
Patent: 5,910,687 →
Application: 08/788,762 →
Wafer Fabrication of Inside-Wrapped Contacts for Electronic Devices
Patent: 5,904,496 →
Application: 08/788,764 →
Integrated Passive Components and Package with Posts
Patent: 6,414,585 →
Application: 08/855,105 →
Electronic Component Package with Posts on the Active Side of the Substrate
Patent: 6,051,489 →
Application: 08/855,106 →
Resistor Fabrication
Patent: 6,121,119 →
Application: 08/865,357 →
Wafer Fabrication of Die Bottom Contacts for Electronic Devices
Patent: 6,221,751 →
Application: 09/105,504 →
Wafer Fabrication of Inside-Wrapped Contacts for Electronic Devices
Patent: 6,355,981 →
Application: 09/235,135 →
Integrated Passive Components and Package with Posts
Patent: 6,954,130 →
Application: 10/071,581 →
Publication: US 2002/0101329
Integrated Passive Components and Package with Posts
Patent: 6,833,986 →
Application: 10/783,673 →
Publication: US 2004/0160727
Integrated Passive Components and Package with Posts
Patent: 6,946,734 →
Application: 10/783,676 →
Publication: US 2004/0160299
Semiconductor with Bottom-Side Wrap-Around Flange Contact
Patent: 7,858,512 →
Application: 12/147,375 →
Publication: US 2009/0321930
Semiconductor with Bottom-Side Wrap-Around Flange Contact
Application: 12/874,412 →
Publication: US 2010/0327448
Related Assignments (1)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jun 21, 2012
From: MARCOUX, PHIL P.; LECKRONE, DANIEL; TECHNOLOGY PROPERTIES LIMITED LLC; WAFER-LEVEL PACKAGING PORTFOLIO LLC
To: MARCOUX, PHIL P.
Reel/Frame 028417/0789 →