IP Library Granted Patent US 6,946,734
Granted Patent B2
US 6,946,734 · App. 10/783,676 · Granted Sep 20, 2005

Integrated passive components and package with posts

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,946,734
App. No.
10/783,676
Granted
Sep 20, 2005
Kind
B2
Abstract

A method and apparatus for an electronic component package of a passive component using wafer level processing;is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.

Claims (19)

1. A packaged diode comprising:

a substrate;

an impurity region implanted in the substrate;

a cathode contact region in contact with the substrate;

an anode contact region in contact with the impurity region;

an insulating layer over a portion of the substrate, so as to expose at least a portion of the cathode contact region and at least a portion of the anode contact region;

an anode post and a cathode post on the insulating layer;

a first conductive layer over the anode post, the first conductive layer extending so as to be in contact with the anode contact region;

a second conductive layer over the cathode post, the second conductive layer extending so as to be in contact with the cathode contact region;

wherein the first conductive layer only covers a portion of a top surface of the anode post; and

wherein the second conductive layer only covers a portion of a top surface of the cathode post.

2. The packaged diode of claim 1 , wherein the substrate is an N-type substrate, and the impurity region is a P-type.

3. The packaged diode of claim 1 , wherein the posts are made of one of the materials selected from: silicon, gallium arsenide, silicon germanium, silicon carbide, gallium phosphide, ceramic materials, sapphire quartz, polymer plastic, patterned plastic, epoxy, glass, Teflon, silicon dioxide, or polysilicon.

4. The packaged diode of claim 1 , wherein he first and second conductive layers are gold.

5. The packaged diode of claim 4 , further comprising a connective layer over the first and second conductive layers, the connecting layer comprising:

a nickel layer; and

a flash gold layer.

6. The packaged diode of claim 1 , further comprising a final passivation layer, the final passivation layer covering portions of the first conductive layer and the second conductive layer, the substrate, and the cathode post and the anode post, so as to expose a top portion of the first conductive layer and a top portion of the second conductive layer.

7. The packaged diode of claim 6 , wherein the final passivation layer is polyimide.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2012
From: MARCOUX, PHIL
To: CHIP SYSTEMS INNOVATIONS, LLC
Reel/Frame 028911/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2012
From: MARCOUX, PHIL P.; LECKRONE, DANIEL; TECHNOLOGY PROPERTIES LIMITED LLC; WAFER-LEVEL PACKAGING PORTFOLIO LLC; ALLIACENSE LIMITED LLC; INTELLASYS BEC LTD.
To: MARCOUX, PHIL P.
Reel/Frame 028417/0789 →
BILL OF SALE Recorded Apr 22, 2010
From: CHIPSCALE, INC.; LECKRONE, DANIEL E.; TECHNOLOGY PROPERTIES LIMITED
To: MARCOUX, PHIL
Reel/Frame 024263/0933 →
NOTICE OF DEFAULT Recorded Oct 8, 2009
From: LECKRONE, DANIEL; TECHNOLOGY PROPERTIES LIMITED; CHIPSCALE, INC.
To: MARCOUX, PHIL
Reel/Frame 023337/0813 →
LICENSE Recorded Mar 4, 2009
From: CHIPSCALE, INC.
To: TECHNOLOGY PROPERTIES LIMITED LLC
Reel/Frame 022343/0281 →
SECURITY AGREEMENT Recorded Jul 17, 2008
From: LECKRONE, DANIEL E.; CHIPSCALE, INC.; TECHNOLOGY PROPERTIES LIMITED
To: MARCOUX, PHIL P.
Reel/Frame 021243/0894 →