Method for fabricating a metal resistor in an IC chip and related structure
View Patent ↗According to one exemplary embodiment, an integrated circuit chip comprises a first interconnect metal layer. The integrated circuit chip further comprises a first intermediate dielectric layer situated over the first interconnect metal layer. The integrated circuit chip further comprises a metal resistor situated over the first intermetallic dielectric layer and below a second intermetallic dielectric layer. The integrated circuit chip further comprises a second interconnect metal layer over the second intermetallic dielectric layer. The integrated circuit chip further comprises a first intermediate via connected to first terminal of the metal resistor, where the first intermediate via is further connected to a first metal segment patterned in the second interconnect metal layer. The integrated circuit chip further comprises a second intermediate via connected to a second terminal of the metal resistor, where the second intermediate via is further connected to a second metal segment patterned in the second interconnect metal layer.
1. An integrated circuit chip formed in a semiconductor substrate, comprising:
a first interconnect metal layer in said semiconductor substrate;
a first intermetallic dielectric layer in said semiconductor substrate situated over said first interconnect metal layer;
a metal resistor in said semiconductor substrate situated over said first intermetallic dielectric layer, said metal resistor being only connected to a second interconnect metal layer;
a dielectric cap layer in said semiconductor substrate patterned on said metal resistor;
a second intermetallic dielectric layer in said semiconductor substrate formed over said dielectric cap layer and said metal resistor;
said second interconnect metal layer in said semiconductor substrate being situated over said second interinetallic dielectric layer;
a first intermediate via in said semiconductor substrate connected to a first terminal of said metal resistor, said first intermediate via being further connected to a first metal segment patterned in said second interconnect metal layer;
a second intermediate via in said semiconductor substrate connected to a second terminal of said metal resistor, said second intermediate via being further connected to a second metal segment patterned in said second interconnect metal layer.
2. The integrated circuit chip of claim 1 wherein said metal resistor is selected from the group consisting of titanium nitride and tantalum nitride.
3. The integrated circuit chip of claim 1 wherein said first interconnect metal layer comprises aluminum.
4. The integrated circuit chip of claim 1 wherein said first intermetallic dielectric layer comprises HDPCVD silicon dioxide.
5. The integrated circuit chip of claim 1 wherein said second intermetallic dielectric layer comprises undoped silica glass.
6. The integrated circuit chip of claim 1 wherein said dielectric cap layer comprises silicon nitride.
7. The integrated circuit chip of claim 1 further comprising an oxide cap layer situated between said metal resistor and said first intermetallic dielectric layer.
8. The integrated circuit chip of claim 7 wherein said oxide cap layer comprises PECVD silicon dioxide.
9. The integrated circuit chip of claim 1 wherein said metal resistor is not connected from below.
10. The integrated circuit chip of claim 1 wherein the thickness of said metal resistor is approximately 100.0 Angstroms to 1500.0 Angstroms.
11. An integrated circuit chip formed in a semiconductor substrate, comprising:
a first interconnect metal layer in said semiconductor substrate;
a first intermetallic dielectric layer in said semiconductor substrate situated over said first interconnect metal layer;
a metal resistor in said semiconductor substrate situated over said first intermetallic dielectric layer, said metal resistor being only connected to a second interconnect metal layer;
a dielectric cap layer in said semiconductor substrate patterned on said metal resistor;
a second intermetallic dielectric layer in said semiconductor substrate formed over said dielectric cap layer and said metal resistor;
said second interconnect metal layer in said semiconductor substrate being situated over said second intermetallic dielectric layer;
a first intermediate via in said semiconductor substrate connected to a first terminal of said metal resistor and said second interconnect metal layer;
a second intermediate via in said semiconductor substrate connected to a second terminal of said metal resistor and said second interconnect metal layer.
12. The integrated circuit chip of claim 11 wherein said metal resistor is selected from the group consisting of titanium nitride and tantalum nitride.
13. The integrated circuit chip of claim 11 wherein said first intermetallic dielectric layer comprises HDPCVD silicon dioxide.
14. The integrated circuit chip of claim 11 wherein said second intermetallic dielectric layer comprises undoped silica glass.
15. The integrated circuit chip of claim 11 wherein said dielectric cap layer comprises silicon nitride.
16. The integrated circuit chip of claim 11 wherein said first interconnect metal layer comprises aluminum.
17. The integrated circuit chip of claim 11 further comprising an oxide cap layer situated between said metal resistor and said first intermetallic dielectric layer.
18. The integrated circuit chip of claim 17 wherein said oxide cap layer comprises PECVD silicon dioxide.
19. The integrated circuit chip of claim 11 wherein said metal resistor is not connected from below.
20. The integrated circuit chip of claim 11 wherein the thickness of said metal resistor is approximately 100.0 Angstroms to 1500.0 Angstroms.