Patent Assignment
Reel/Frame 065284/0123
Release of Security Interest
Recorded: 2023-10-18
Pages: 18
Assignor
Assignee
NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR OPERATING COMPANY
4321 JAMBOREE ROAD, NEWPORT BEACH, CALIFORNIA, 92660
Covered Properties
(175)
Ion Etching Process with Minimized Redeposition
Patent:
4,396,479 →
Application:
06/355,445 →
Process for and Structure of High Density Vlsi Circuits, Having Self- Aligned Gates and Contacts for Fet Devices and Conducting Lines
Patent:
4,477,962 →
Application:
06/397,050 →
Process for and Structure of High Density Vlsi Circuits, Having Self- Aligned Gates and Contacts for Pet Devices and Conducting Lines
Patent:
4,506,437 →
Application:
06/397,052 →
High Rate Resist Polymerization Apparatus
Patent:
4,459,937 →
Application:
06/397,646 →
Reactive Ion Etching of Moltybdenum Silicide and N Polysilicon
Patent:
4,444,617 →
Application:
06/456,183 →
Dimension Monitoring Technique for Semiconductor Fabrication
Patent:
4,639,142 →
Application:
06/484,666 →
Method for Making a Reliable Ohmic Contact Between Two Layers of Integrated Circuit Metallizations
Patent:
4,507,852 →
Application:
06/531,529 →
Small Area High Value Resistor with Greatly Reduced Parasitic Capacitance
Patent:
4,497,685 →
Application:
06/544,914 →
Two-Level Transistor Structures and Method Utilizing Minimal Area Therefor
Patent:
4,593,453 →
Application:
06/621,773 →
Production of Oxy-Metallo-Organic Polymer
Patent:
4,698,417 →
Application:
06/831,955 →
Diffused Field Cmos-Bulk Process
Patent:
4,749,662 →
Application:
06/837,560 →
Method of Making Hardened Nmos Sub-Micron Field Effect Transistors
Patent:
4,697,328 →
Application:
06/856,302 →
Method of Making Hardened Cmos Sub-Micron Field Effect Transistors
Patent:
4,694,565 →
Application:
06/856,304 →
Lateral Transistor Separated from Substrate by Intersecting Slots Filled with Substrate Oxide for Minimal Interference Therefrom
Patent:
5,031,014 →
Application:
07/062,007 →
Extremely Small Area Npn Lateral Transistor
Patent:
5,043,787 →
Application:
07/066,593 →
Pnp Type Lateral Transistor with Minimal Substrate Operation Interference
Patent:
5,047,828 →
Application:
07/066,663 →
Complementary Npn and Pnp Lateral Transistors Separated from Substrate by Intersecting Slots Filled with Substrate Oxide for Minimal Interference Therefrom
Patent:
5,097,316 →
Application:
07/068,383 →
Sub-Micron Devices with Method for Forming Sub-Micron Contacts
Patent:
4,947,225 →
Application:
07/073,591 →
Diffused Field Cmos-Bulk Process and Cmos Transistors
Patent:
4,879,583 →
Application:
07/105,413 →
Damascene Metalliztion Process and Structure
Patent:
6,445,073 →
Application:
09/002,326 →
Physical Vapor Deposition Chamber
Patent:
5,935,397 →
Application:
09/070,314 →
Apparaus for Reducing Cool Chamber Particles
Patent:
6,119,368 →
Application:
09/070,372 →
Dual-Damascene Interconnect Structures Employing Low-K Dielectric Materials
Patent:
6,627,539 →
Application:
09/149,910 →
Interconnect with Low Dielectric Constant Insulators for Semiconductor Integrated Circuit Manufacturing
Patent:
6,187,672 →
Application:
09/158,337 →
Method for Fabricating Interpoly Dielectrics in Non-Volatile Stacked-Gate Memory Structures
Patent:
6,339,000 →
Application:
09/160,834 →
Methods for Forming High-Performing Dual-Damascene Interconnect Structures
Patent:
6,071,809 →
Application:
09/161,176 →
Nitride Etch Stop for Poisoned Unlanded Vias
Patent:
6,239,026 →
Application:
09/162,185 →
Elevated Channel Mosfet
Patent:
6,143,593 →
Application:
09/162,272 →
Improved Methods for Barrier Layer Formation
Patent:
6,255,192 →
Application:
09/163,135 →
Ic Interconnect Structures and Methods for Making Same
Patent:
6,245,663 →
Application:
09/163,967 →
Interconnect Structure and Method Employing Air Gaps Between Metal Lines and Between Metal Layers
Patent:
6,211,561 →
Application:
09/193,499 →
Dual-Damascene Interconnect Structures and Methods of Fabricating Same
Patent:
6,417,094 →
Application:
09/224,339 →
Thin-Film Capacitors and Methods for Forming the Same
Patent:
6,180,976 →
Application:
09/241,728 →
Methods and Apparatus for Stripping Photoresist and Polymer Layers from a Semiconductor Stack in a Non-Corrosive Environment
Patent:
6,251,568 →
Application:
09/247,234 →
Method and Apparatus for High-Resolution in-Situ Plasma Etching of Inorganic and Metal Films
Patent:
6,291,361 →
Application:
09/275,628 →
Interconnect with Low Dielectric Constant Insulators for Semiconductor Integrated Circuit Manufacturing
Patent:
6,787,911 →
Application:
09/317,536 →
Method for Dual Damascene Process Using Electron Beam and Ion Implantation Cure Methods for Low Dielectric Constant Materials
Patent:
6,271,127 →
Application:
09/329,569 →
Semiconductor Device Having a Passivation Layer and Method for Its Fabrication
Patent:
6,475,895 →
Application:
09/369,982 →
Anti-Reflective Coating and Process Using an Anti-Reflective Coating
Patent:
6,924,196 →
Application:
09/370,508 →
Microelectronic Interconnect Structures and Methods for Forming the Same
Patent:
6,225,681 →
Application:
09/390,445 →
Title Not Available
Patent:
6,261,918 →
Application:
09/411,807 →
Method and Apparatus for Pre-Conditioning Flash Memory Devices
Patent:
6,233,178 →
Application:
09/418,399 →
Method of Fabricating Semiconductor Devices Using Shallow Trench Isolation with Reduced Narrow Channel Effect
Patent:
6,284,623 →
Application:
09/427,407 →
Semiconductor Device and Process
Patent:
6,383,821 →
Application:
09/430,729 →
Dielectric Material Suitable for Microelectronic Circuits and Method of Forming Same
Patent:
6,280,794 →
Application:
09/432,046 →
Bonding Pad and Support Structure and Method for Their Fabrication
Patent:
6,198,170 →
Application:
09/465,532 →
Pre-Clean Chamber
Patent:
6,602,793 →
Application:
09/497,360 →
Transparent Phase Shift Mask for Fabrication of Small Feature Sizes
Patent:
6,479,194 →
Application:
09/499,244 →
Method For Fabrication And Structure For High Aspect Ratio Vias
Patent:
6,329,290 →
Application:
09/512,396 →
Method for fabrication of ceramic tantalum nitride and improved structures based thereon
Patent:
6,251,796 →
Application:
09/512,397 →
Fabrication of Improved Low-K Dielectric Structures
Patent:
6,444,136 →
Application:
09/559,292 →
Method for fabrication of damascene interconnects and related structures
Patent:
6,380,078 →
Application:
09/569,890 →
Method for Selective Fabrication of High Capacitance Density Areas in a Low Dielectric Constant Material
Patent:
7,049,246 →
Application:
09/575,055 →
Structure and Method for Fabrication of an Improved Capacitor
Patent:
6,411,492 →
Application:
09/578,229 →
Method and Apparatus for Improving a Dark Field Inspection Environment
Patent:
6,490,032 →
Application:
09/583,593 →
Double-Implant High Performance Varactor and Method for Manufacturing Same
Patent:
6,995,068 →
Application:
09/590,462 →
Technique for reducing 1/F noise in mosfets
Patent:
6,514,825 →
Application:
09/606,778 →
Elevated Channel Mosfet
Patent:
6,630,710 →
Application:
09/616,233 →
Method for Fabrication of on-Chip Inductors and Related Structures
Patent:
6,309,922 →
Application:
09/627,505 →
Method for Fabrication of High Inductance Inductors and Related Structure
Patent:
6,417,755 →
Application:
09/649,442 →
Bipolar Transistor with Reduced Base Resistance
Patent:
6,410,975 →
Application:
09/653,982 →
Method for Fabricating on-Chip Inductors and Related Structure
Patent:
6,396,122 →
Application:
09/658,483 →
Damascene Interconnect Structure and Fabrication Method Having Air Gaps Between Metal Lines and Metal Layers
Patent:
6,984,577 →
Application:
09/665,422 →
Method for independent control of polycrystalline silicon-germanium in a silicon-germanium HBT and related structure
Patent:
6,365,479 →
Application:
09/667,274 →
Method for elimination of contaminants prior to epitaxy
Patent:
6,514,886 →
Application:
09/667,660 →
Method for Increasing Inductance of on-Chip Inductors and Related Structure
Patent:
6,534,406 →
Application:
09/668,790 →
Apparatus for high-resolution in-situ plasma etching of inorganic and metal films
Patent:
6,328,848 →
Application:
09/671,928 →
Structure for Reduction of Base and Emitter Resistance and Related Method
Patent:
6,486,532 →
Application:
09/677,707 →
Method for Reducing Contamination Prior to Epitaxial Growth and Related Structure
Patent:
6,444,591 →
Application:
09/677,708 →
Method of Fabricating an Interconnect Structure Employing Air Gaps Between Metal Lines and Between Metal Layers
Patent:
7,056,822 →
Application:
09/686,323 →
Structure for Bonding Pad and Method for Its Fabrication
Patent:
6,740,985 →
Application:
09/716,350 →
Method for Fabricating Interfacial Oxide in a Transistor and Related Structure
Patent:
6,638,819 →
Application:
09/721,128 →
Method for Fabrication of an Mim Capacitor and Related Structure
Patent:
6,430,028 →
Application:
09/721,342 →
Method for Fabricating a Self-Aligned Emitter in a Bipolar Transistor
Patent:
6,534,372 →
Application:
09/721,344 →
Method for Controlling Critical Dimension in a Polycrystalline Silicon Emitter and Related Structure
Patent:
6,620,732 →
Application:
09/721,551 →
On-Chip Inductors
Method for Fabrication of Ceramic Tantalum Nitride and Imporoved Structures Based Thereon
Thin-film capacitors and methods for forming the same
High Performance Bipolar Transistor
Low Cost Fabrication of High Resistivity Resistors
Method for Reducing Base to Collector Capacitance and Related Structure
Patent:
6,534,802 →
Application:
09/850,028 →
Method for Opening a Semiconductor Region for Fabricating an Hbt
Patent:
6,746,928 →
Application:
09/851,228 →
Method to Reduce Emitter to Base Capacitance and Related Structure
Patent:
6,444,535 →
Application:
09/852,183 →
Method for Fabricating Lateral Pnp Heterojunction Bipolar Transistor and Related Structure
Patent:
6,459,104 →
Application:
09/853,735 →
Method and Apparatus for High-Resolution in-Situ Plasma Etching of Inorganic and Metal Films
Microelectronic Air-Gap Structures and Methods of Forming the Same
Reduced 1/F Noise in Mosfets
Method for Independent Control of Polycrystalline Silicon-Germanium in an Hbt
Independent Control of Polycrystalline Silicon-Germanium in an Hbt and Related Structure
Band Gap Compensated Hbt
Method and Structure for Eliminating Collector-Base Band Gap Discontinuity in an Hbt
Structure for a Selective Epitaxial Hbt Emitter
Patent:
6,617,619 →
Application:
10/067,034 →
Method for Controlling Critical Dimension in an Hbt Emitter and Related Structure
Patent:
6,597,022 →
Application:
10/067,159 →
Method for Fabricating a Metal Resistor in an Ic Chip and Related Structure
Method for Controlling an Emitter Window Opening in an Hbt and Related Structure
Patent:
6,586,307 →
Application:
10/075,701 →
Elimination of Contaminants Prior to Epitaxy and Related Structure
Patent:
6,580,104 →
Application:
10/114,749 →
Method for Reducing Base Resistance in a Bipolar Transistor
Reduced Base Resistance in a Bipolar Transistor
Method for Integrating a Metastable Base into a High-Performance Hbt and Related Structure
Patent:
6,586,297 →
Application:
10/160,979 →
A Bipolar Transistor and Related Structure
Patent:
6,683,366 →
Application:
10/163,386 →
Method and System for Fabricating a Bipolar Transistor and Related Structure
Patent:
6,589,850 →
Application:
10/163,661 →
Fabrication of High-Density Capacitors for Mixed Signal/Rf Circuits
Patent:
7,060,557 →
Application:
10/190,297 →
Damascene Trench Capacitor for Mixed-Signal/Rf Ic Applications
Patent:
6,838,352 →
Application:
10/190,459 →
Method for Reducing Contamination Prior to Epitaxial Growth and Related Structure
A Bipolar Transistor with Reduced Emitter to Base Capacitance
Electrostatic Discharge Clamp
Patent:
6,927,957 →
Application:
10/199,750 →
Method for Fabricating a Self-Aligned Bipolar Transistor and Related Structure
Patent:
6,784,467 →
Application:
10/218,527 →
Method for Forming Cmos Transistor Spacers in a Bicmos Process and Related Structure
Patent:
6,830,967 →
Application:
10/262,714 →
An Hbt Having a Controlled Emitter Window Opening
Patent:
6,765,243 →
Application:
10/265,334 →
Temperature Insensitive Resistor in an Ic Chip
Patent:
6,759,729 →
Application:
10/272,888 →
Interfacial Oxide in a Transistor
Patent:
6,787,879 →
Application:
10/289,821 →
Reducing Extrinsic Base Resistance and Improving Manufacturability in an Npn Transistor
Patent:
6,893,931 →
Application:
10/290,955 →
High Gain Bipolar Transistor
Method for Reducing Extrinsic Base Resistance and Improving Manufacturability in an Npn Transistor
Patent:
6,830,982 →
Application:
10/290,976 →
Transparent Phase Shift Mask for Fabrication of Small Feature Sizes
Patent:
6,716,558 →
Application:
10/291,116 →
Method for Eliminating Collector-Base Band Gap in an Hbt
Patent:
6,673,688 →
Application:
10/301,885 →
Method for Fabricating a Selective Epitaxial Hbt Emitter
Patent:
6,680,235 →
Application:
10/302,308 →
Method for Fabricating a Self-Aligned Emitter in a Bipolar Transistor
Patent:
6,716,711 →
Application:
10/308,661 →
A Metastable Base in a High-Performance Hbt
Patent:
6,781,214 →
Application:
10/313,508 →
Efficiently fabricated bipolar transistor
Patent:
6,972,442 →
Application:
10/313,583 →
System for Fabricating a Bipolar Transistor
Patent:
6,830,625 →
Application:
10/313,700 →
Probe Card and Probe Needle for High Frequency Testing
Patent:
6,727,716 →
Application:
10/320,334 →
Polycrystalline Silicon Emitter Having an Accurately Controlled Critical Dimension
Patent:
6,965,132 →
Application:
10/321,877 →
Bifet Voltage Controlled Oscillator
Method for Patterning Densely Packed Metal Segments in a Semiconductor Die and Related Structure
Method for Controlling Critical Dimension in an Hbt Emitter
Patent:
6,818,520 →
Application:
10/364,550 →
Method for Controlling an Emitter Window Opening in an Hbt and Related Structure
Patent:
6,764,913 →
Application:
10/369,027 →
Method for Forming Deep Trench Isolation and Related Structure
Patent:
7,015,115 →
Application:
10/371,307 →
Method for Hard Mask Removal for Deep Trench Isolation and Related Structure
Patent:
6,770,541 →
Application:
10/371,416 →
Method for Fabricating a Bipolar Transistor in a Bicmos Process and Related Structure
Patent:
6,797,580 →
Application:
10/371,706 →
Method for Improved Alignment Tolerance in a Bipolar Transistor
Patent:
6,812,107 →
Application:
10/375,727 →
High Density Composite Mim Capacitor with Reduced Voltage Dependence in Semiconductor Dies
Patent:
6,680,521 →
Application:
10/410,937 →
Transparent Phase Shift Mask for Fabrication of Small Feature Sizes
Patent:
6,933,085 →
Application:
10/431,073 →
Technique for Reducing Contaminants in Fabrication of Semiconductor Wafers
Patent:
7,064,073 →
Application:
10/434,961 →
Method for Fabrication of Sige Layer Having Small Poly Grains and Related Structure
Method for Fabrication of Emitter of a Transistor and Related Structure
Patent:
6,797,578 →
Application:
10/437,723 →
Method for Fabricating a Self-Aligned Bipolar Transistor Having Increased Manufacturability and Related Structure
Method for Fabricating a Self-Aligned Bipolar Transistor with Planarizing Layer and Related Structure
Self-Aligned Bipolar Transistor Having Recessed Spacers and Method for Fabricating Same
Self-Aligned Bipolar Transistor Without Spacers and Method for Fabricating Same
Patent:
6,867,440 →
Application:
10/442,501 →
High Density Composite Mim Capacitor with Flexible Routing in Semiconductor Dies
Patent:
6,777,777 →
Application:
10/447,397 →
Method for Fabricating a High Density Composite Mim Capacitor with Reduced Voltage Dependence in Semiconductor Dies
Patent:
7,041,569 →
Application:
10/712,067 →
Circuit for Detecting Arcing in an Etch Tool During Wafer Processing
Patent:
7,063,988 →
Application:
10/758,494 →
Composite Ground Shield for Passive Components in a Semiconductor Die
Patent:
7,154,161 →
Application:
10/826,507 →
Deep Trench Isolation Region with Reduced-Size Cavities in Overlying Field Oxide
Patent:
6,995,449 →
Application:
10/842,943 →
Composite Series Resistor Having Reduced Temperature Sensitivity in an Ic Chip
Patent:
7,078,786 →
Application:
10/843,190 →
Method for Fabricating a High Density Composite Mim Capacitor with Flexible Routing in Semiconductor Dies
Patent:
7,078,310 →
Application:
10/850,187 →
Method for Fabricating a Self-Aligned Bipolar Transistor Having Recessed Spacers
Patent:
7,033,898 →
Application:
10/865,153 →
Npn Transistor Having Reduced Extrinisic Base Resistance and Improved Manufacturability
Patent:
7,064,361 →
Application:
10/865,634 →
Method for Fabricating a Self-Aligned Bipolar Transistor
Patent:
7,041,564 →
Application:
10/870,900 →
Transistor Emitter Having Alternating Undoped and Doped Layers
Patent:
7,078,744 →
Application:
10/888,406 →
Bipolar Transistor Fabricated in a Bicmos Process
Patent:
7,994,611 →
Application:
10/892,015 →
Sige Layer Having Small Poly Grains
Patent:
7,132,700 →
Application:
10/915,797 →
Cmos Transistor Spacers Formed in a Bicmos Process
Patent:
6,992,338 →
Application:
10/936,927 →
Method for Fabricating a Self-Aligned Bipolar Transistor Without Spacers
Patent:
7,282,418 →
Application:
10/952,256 →
Method for Opto-Electronic Integration on a Soi Substrate and Related Structure
Patent:
7,338,848 →
Application:
10/970,645 →
Selective Fabrication of High Capacitance Density Areas in a Low Dielectric Constant Material
Patent:
7,109,125 →
Application:
10/995,762 →
Self-Aligned Bipolar Transistor Having Increased Manufacturability
Patent:
7,064,415 →
Application:
10/995,769 →
Method and Structure for Integration of Phosphorus Emitter in an Npn Device in a Bicmos Process
Patent:
7,297,992 →
Application:
10/997,534 →
Method for Fabricating a Mim Capacitor Having Increased Capacitance Density and Related Structure
Npn Transistor Having Reduced Extrinsic Base Resistance and Improved Manufacturability
Patent:
7,235,861 →
Application:
11/003,572 →
Soi Substrate for Integration of Opto-Electronics with Sige Bicmos
Patent:
7,339,254 →
Application:
11/018,164 →
Integration of Sige Npn and Vertical Pnp Devices on a Substrate
Patent:
7,541,231 →
Application:
11/084,391 →
Method for Effective Bicmos Process Integration
Patent:
7,335,547 →
Application:
11/086,168 →
Densely Packed Metal Segments Patterned in a Semiconductor Die
Method for Fabricating a Mim Capacitor High-K Dielectric for Increased Capacitance Density and Related Structure
Selective and Non-Selective Epitaxy for Base Integration in a Bicmos Process and Related Structure
Patent:
7,291,898 →
Application:
11/146,537 →
Fabricating a Self-Aligned Bipolar Transistor Having Increased Manufacturability
Patent:
7,291,536 →
Application:
11/175,720 →
Deep N wells in triple well structures
Patent:
9,136,157 →
Application:
11/198,425 →
Integration of Phosphorus Emitter in an Npn Device in a Bicmos Process
Patent:
7,498,620 →
Application:
11/525,457 →
Structure for Encapsulating Microelectronic Devices
Patent:
8,212,351 →
Application:
11/542,088 →
Method for Fabricating a Frontside Through-Wafer via in a Processed Wafer and Related Structure
Patent:
7,704,874 →
Application:
11/641,500 →
Method for Fabricating a Top Conductive Layer in a Semiconductor Die and Related Structure
Patent:
7,589,009 →
Application:
11/641,925 →
Metal Resistor
Application:
60/276,277 →
Method for fabricating a backside through-wafer via in a processed wafer and related structure
Application:
60/848,973 →