Electrostatic discharge clamp
According to one exemplary embodiment, an ESD bus clamp in an integrated circuit comprises an inverter having an input and an output. The ESD bus clamp further comprises a bipolar transistor having a base, an emitter, and a collector, where the base is connected to the output of the inverter, the emitter is connected to a ground of the integrated circuit, and the collector is connected to a power bus of the integrated circuit. The bipolar transistor, for example, may be an NPN bipolar transistor and may begin shunting current to the ground when an ESD discharge causes a voltage level on the power bus to increase by approximately 1.0 volt. According to this exemplary embodiment, the ESD bus clamp further comprises a resistor coupling the input of the inverter to the power bus. The ESD bus clamp further comprises a capacitor coupling the input of the inverter to ground.
1. An ESD bus clamp in an integrated circuit, said ESD bus clamp comprising:
an inverter having an input and an output;
a bipolar transistor having a base, an emitter, and a collector, said base being connected to said output of said inverter, said emitter being connected to a ground of said integrated circuit, said collector being directly connected to a power bus of said integrated circuit;
a resistor coupling said input of said inverter to said power bus;
a capacitor coupling said input of said inverter to said ground;
wherein said bipolar transistor shunts current to said ground when an ESD discharge causes a voltage level on said power bus to increase by approximately 1.0 volt, wherein said ESD bus clamp limits an approximately 2.0 kilovolt discharge to approximately 5.0 volts.
2. The ESD bus clamp of claim 1 wherein said ground is connected to a substrate of said integrated circuit.
3. The ESD bus clamp of claim 1 wherein said bipolar transistor is an NPN bipolar transistor.
4. The ESD bus clamp of claim 1 wherein said power bus is a Vdd bus.
5. The ESD bus clamp of claim 1 wherein said resistor comprises at least one FET.
6. The ESD bus clamp of claim 1 wherein said capacitor comprises at least one FET.
7. An ESD bus clamp in an integrated circuit, said ESD bus clamp comprising:
a plurality of inverters, each of said plurality of inverters having a respective input and a respective output;
a plurality of bipolar transistors, each of said plurality of bipolar transistors having a base, an emitter, and a collector, said base of said each of said plurality of bipolar transistors being coupled to said respective output of one of said plurality of inverters, said emitter of said each of said plurality of bipolar transistors being coupled to a ground of said integrated circuit, said collector of said each of said plurality of bipolar transistors being directly coupled to a power bus of said integrated circuit, wherein each of said plurality of bipolar transistors is a segment of a single bipolar transistor;
a resistor coupling said respective input of said each of said plurality of inverters to said power bus;
a first capacitor coupling said respective input of said each of said plurality of inverters to said ground;
wherein said plurality of bipolar transistors shunt current to said ground when an ESD discharge causes a voltage level on said power bus to increase by approximately 1.0 volt, wherein said ESD bus clamp limits an approximately 2.0 kilovolt discharge to approximately 5.0 volts.
8. The ESD bus clamp of claim 7 further comprising a second capacitor coupling said power bus to said ground.
9. The ESD bus clamp of claim 7 wherein said ground is connected to a substrate of said integrated circuit.
10. The ESD bus clamp of claim 7 wherein each of said plurality of bipolar transistors is an NPN bipolar transistor.
11. The ESD bus clamp of claim 7 wherein said power bus is a Vdd bus.
12. The ESD bus clamp of claim 7 wherein said resistor comprises at least one FET.
13. The ESD bus clamp of claim 7 wherein said first capacitor comprises at least one FET.
14. The ESD bus clamp of claim 8 wherein said second capacitor comprises at least one FET.
15. The ESD bus clamp of claim 7 wherein said plurality of bipolar transistors comprises NPN bipolar transistors.
16. An ESD protection circuit in an integrated circuit, said ESD protection circuit comprising:
an ESD bus clamp comprising:
at least one inverter having an input and an output;
at least one bipolar transistor having a base, an emitter, and a collector, said base being connected to said output of said at least one inverter, said emitter being connected to a ground of said integrated circuit, said collector being connected to a power bus of said integrated circuit;
a resistor coupling said input of said at least one inverter to said power bus;
a capacitor coupling said input of said at least one inverter to said ground;
a first diode having a cathode terminal connected to said power bus and an anode terminal connected to a signal line in said integrated circuit;
a second diode having a cathode terminal connected to said signal line and an anode terminal connected to said ground;
a third diode having a cathode connected to said power bus and an anode connected to said ground.
17. The ESD protection circuit of claim 16 wherein said ground is connected to a substrate of said integrated circuit.
18. The ESD protection circuit of claim 16 wherein said at least one bipolar transistor is an NPN bipolar transistor.
19. The ESD protection circuit of claim 16 wherein said power bus is a Vdd bus.
20. The ESD protection circuit of claim 16 wherein said resistor comprises at least one FET.
21. The ESD protection circuit of claim 16 wherein said capacitor comprises at least one FET.
22. The ESD protection circuit of claim 16 wherein said at least one bipolar transistor shunts current to said ground when an ESD discharge causes a voltage level on said power bus to increase by approximately 1.0 volt.
23. The ESD protection circuit of claim 16 wherein said first diode and said third diode are N-well diodes.
24. The ESD protection circuit of claim 16 wherein said second diode is a substrate diode.