NPN transistor having reduced extrinsic base resistance and improved manufacturability
View Patent ↗According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction bipolar transistor. The base layer can be, for example, silicon-germanium. According to this exemplary embodiment, the NPN bipolar transistor further comprises a cap layer situated over the base layer, where a portion of the cap layer is situated over the extrinsic base region, and where the portion of the cap layer situated over the extrinsic base region comprises an indium dopant. The cap layer may be, for example, polycrystalline silicon. According to this exemplary embodiment, the NPN bipolar transistor may further comprise an emitter situated over the intrinsic base region. The emitter may be, for example, polycrystalline silicon.
1. An NPN bipolar transistor comprising:
a base layer situated over a collector, said base layer comprising an intrinsic base region and an extrinsic base region;
a cap layer situated over said base layer, said cap layer having a first portion situated over said extrinsic base region and a second portion situated over said intrinsic base region, only said first portion of said cap layer situated over said extrinsic base region comprising an implanted indium dopant, said implanted indium dopant having a reduced diffusion rate in said extrinsic base region;
wherein said reduced diffusion rate of said implanted indium dopant causes a reduction in resistance of said extrinsic base region.
2. The NPN bipolar transistor of claim 1 further comprising an emitter situated over said intrinsic base region.
3. The NPN bipolar transistor of claim 1 wherein said base layer comprises silicon-germanium.
4. The NPN bipolar transistor of claim 1 wherein said cap layer comprises polycrystalline silicon.
5. The NPN bipolar transistor of claim 1 wherein said NPN bipolar transistor is an NPN silicon-germanium heterojunction bipolar transistor.
6. The NPN bipolar transistor of claim 2 wherein said emitter comprises polycrystalline silicon.
7. The NPN bipolar transistor of claim 1 wherein said indium dopant extends to a depth of between approximately 10.0 Angstroms and approximately 100.0 Angstroms in said first portion of said cap layer situated over said extrinsic base region.
8. The NPN bipolar transistor of claim 1 wherein a thickness of said cap layer is less than 100.0 Angstroms.
9. An NPN bipolar transistor comprising:
a base layer situated over a collector, said base layer comprising an intrinsic base region and an extrinsic base region;
an emitter situated over said intrinsic base region of said base layer;
a cap layer situated over said base layer, said cap layer having a first portion situated over said extrinsic base region and a second portion situated over said intrinsic base region, only said first portion of said cap layer situated over said extrinsic base region comprising an implanted indium dopant, said implanted indium dopant having a reduced diffusion rate in said extrinsic base region;
wherein said reduced diffusion rate of said implanted indium dopant causes a reduction in resistance of said extrinsic base region.
10. The NPN bipolar transistor of claim 9 wherein said base layer comprises silicon-germanium.
11. The NPN bipolar transistor of claim 9 wherein said cap layer comprises polycrystalline silicon.