IP Library Granted Patent US 7,078,744
Granted Patent B1
US 7,078,744 · App. 10/888,406 · Granted Jul 18, 2006

Transistor emitter having alternating undoped and doped layers

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Quick Facts
Patent No.
US 7,078,744
App. No.
10/888,406
Granted
Jul 18, 2006
Kind
B1
Abstract

A disclosed embodiment is a method for fabricating an emitter structure, comprising a step of conformally depositing an undoped polysilicon layer in an emitter window opening and over a base. Next, a doped polysilicon layer is non-conformally deposited over the undoped layer. Thereafter, the steps of conformally depositing an undoped polysilicon layer and non-conformally depositing a doped polysilicon layer are repeated until the emitter window opening is filled. The method can further comprise a step of activating dopants. In another embodiment, an emitter structure is fabricated according to the above method.

Claims (12)

1. A structure in a semiconductor substrate comprising:

a base;

a plurality of undoped emitter layers situated over said base layer, each of said plurality of undoped emitter layers comprising an undoped bottom and an undoped sidewall;

a plurality of doped emitter layers, each of said plurality of doped emitter layers being situated over a corresponding one of said plurality of undoped emitter layers, each of said plurality of doped emitter layers comprising a doped bottom and a doped sidewall;

said plurality of undoped emitter layers and said plurality of doped emitter layers forming an emitter.

2. The structure of claim 1 wherein each of said plurality of undoped emitter layers comprises undoped polysilicon.

3. The structure of claim 1 wherein each of said plurality of doped emitter layers comprises N type polysilicon.

4. The structure of claim 1 wherein each of said plurality of undoped emitter layers is conformal in relation to an emitter window opening.

5. The structure of claim 1 wherein each of said plurality of undoped emitter layers has a bottom thickness and a sidewall thickness, wherein said bottom thickness is approximately equal to said sidewall thickness.

6. The structure of claim 1 wherein each of said plurality of doped emitter layers is non-conformal in relation to an emitter window opening.

7. The structure of claim 1 wherein each of said plurality of doped emitter layers has a bottom thickness and a sidewall thickness, wherein said bottom thickness is greater than said sidewall thickness.

8. The structure of claim 7 wherein said bottom thickness is equal to approximately twice said sidewall thickness.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Oct 18, 2023
From: WELLS FARGO CAPITAL FINANCE, LLC, AS SUCCESSOR BY MERGER TO WACHOVIA CAPITAL FINANCE CORPORATION (WESTERN)
To: NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR OPERATING COMPANY
Reel/Frame 065284/0123 →
FIRST AMENDMENT TO PATENT SECURITY AGREEMENT Recorded Apr 4, 2007
From: NEWPORT FAB, LLC
To: WACHOVIA CAPITAL FINANCE CORPORATION (WESTERN)
Reel/Frame 019111/0295 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2005
From: U'REN, GREG D.
To: NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR
Reel/Frame 016634/0322 →