Patent Assignment
Reel/Frame 019111/0295
First Amendment to Patent Security Agreement
Recorded: 2007-04-04
Received: 2007-04-04
Pages: 12
Assignor
NEWPORT FAB, LLC
Executed: 2007-02-28
Assignee
WACHOVIA CAPITAL FINANCE CORPORATION (WESTERN)
251 S. LAKE AVE., SUITE 900, PASADENA, CA, 91101, UNITED STATES
Covered Properties
(46)
Method for Fabricating a Top Conductive Layer in a Semiconductor Die and Related Structure
Application:
11/641,925 →
Method for Fabricating a Frontside Through-Wafer via in a Processed Wafer and Related Structure
Application:
11/641,500 →
Structure for Encapsulating Microelectronic Devices
Application:
11/542,088 →
Method for fabricating a backside through-wafer via in a processed wafer and related structure
Application:
60/848,973 →
Integration of Phosphorus Emitter in an Npn Device in a Bicmos Process
Application:
11/525,457 →
Deep N wells in triple well structures
Application:
11/198,425 →
Fabricating a Self-Aligned Bipolar Transistor Having Increased Manufacturability
Application:
11/175,720 →
Selective and Non-Selective Epitaxy for Base Integration in a Bicmos Process and Related Structure
Application:
11/146,537 →
Method for Fabricating a Mim Capacitor High-K Dielectric for Increased Capacitance Density and Related Structure
Application:
11/121,360 →
Densely Packed Metal Segments Patterned in a Semiconductor Die
Application:
11/112,194 →
Method for Effective Bicmos Process Integration
Application:
11/086,168 →
Integration of Sige Npn and Vertical Pnp Devices on a Substrate
Application:
11/084,391 →
Soi Substrate for Integration of Opto-Electronics with Sige Bicmos
Application:
11/018,164 →
Npn Transistor Having Reduced Extrinsic Base Resistance and Improved Manufacturability
Application:
11/003,572 →
Method for Fabricating a Mim Capacitor Having Increased Capacitance Density and Related Structure
Application:
10/997,638 →
Method and Structure for Integration of Phosphorus Emitter in an Npn Device in a Bicmos Process
Application:
10/997,534 →
Selective Fabrication of High Capacitance Density Areas in a Low Dielectric Constant Material
Application:
10/995,762 →
Self-Aligned Bipolar Transistor Having Increased Manufacturability
Application:
10/995,769 →
Method for Opto-Electronic Integration on a Soi Substrate and Related Structure
Application:
10/970,645 →
Method for Fabricating a Self-Aligned Bipolar Transistor Without Spacers
Application:
10/952,256 →
Cmos Transistor Spacers Formed in a Bicmos Process
Application:
10/936,927 →
Sige Layer Having Small Poly Grains
Application:
10/915,797 →
Bipolar Transistor Fabricated in a Bicmos Process
Application:
10/892,015 →
Transistor Emitter Having Alternating Undoped and Doped Layers
Application:
10/888,406 →
Method for Fabricating a Self-Aligned Bipolar Transistor
Application:
10/870,900 →
Npn Transistor Having Reduced Extrinisic Base Resistance and Improved Manufacturability
Application:
10/865,634 →
Method for Fabricating a Self-Aligned Bipolar Transistor Having Recessed Spacers
Application:
10/865,153 →
Method for Fabricating a High Density Composite Mim Capacitor with Flexible Routing in Semiconductor Dies
Application:
10/850,187 →
Deep Trench Isolation Region with Reduced-Size Cavities in Overlying Field Oxide
Application:
10/842,943 →
Composite Series Resistor Having Reduced Temperature Sensitivity in an Ic Chip
Application:
10/843,190 →
Composite Ground Shield for Passive Components in a Semiconductor Die
Application:
10/826,507 →
Circuit for Detecting Arcing in an Etch Tool During Wafer Processing
Application:
10/758,494 →
Method for Fabricating a High Density Composite Mim Capacitor with Reduced Voltage Dependence in Semiconductor Dies
Application:
10/712,067 →
Method for Fabricating a Self-Aligned Bipolar Transistor Having Increased Manufacturability and Related Structure
Application:
10/442,449 →
Technique for Reducing Contaminants in Fabrication of Semiconductor Wafers
Application:
10/434,961 →
Method for Forming Deep Trench Isolation and Related Structure
Application:
10/371,307 →
Polycrystalline Silicon Emitter Having an Accurately Controlled Critical Dimension
Application:
10/321,877 →
Efficiently fabricated bipolar transistor
Application:
10/313,583 →
Damascene Trench Capacitor for Mixed-Signal/Rf Ic Applications
Application:
10/190,459 →
Fabrication of High-Density Capacitors for Mixed Signal/Rf Circuits
Application:
10/190,297 →
Method for Controlling an Emitter Window Opening in an Hbt and Related Structure
Application:
10/075,701 →
Independent Control of Polycrystalline Silicon-Germanium in an Hbt and Related Structure
Application:
10/054,438 →
Method for Measuring Load Between Mcdn Devices for Use in Determining Path with Optimal Throughput
Application:
09/920,081 →
Low Cost Fabrication of High Resistivity Resistors
Application:
09/833,953 →
Metal Resistor
Application:
60/276,277 →
On-Chip Inductors
Application:
09/754,806 →